GICR_IPRIORITYR<n>E Interrupt Priority Registers (extended PPI range) when GICv3.1 is implemented 8 23 GIC Redistributor SGI_base 0x0400 + (4 * n) GICR_IPRIORITYR<n>E RW Holds the priority of the corresponding interrupt for each extended PPI supported by the GIC. GICR A copy of this register is provided for each Redistributor. GICR_IPRIORITYR<n>E is a 32-bit register. Priority_offset_3B 31 24 31:24 Interrupt priority value from an IMPLEMENTATION DEFINED range, at byte offset 3. Lower priority values correspond to greater priority of the interrupt. For an INTID configured as non-maskable, this field is RES0. AU Priority_offset_2B 23 16 23:16 Interrupt priority value from an IMPLEMENTATION DEFINED range, at byte offset 2. Lower priority values correspond to greater priority of the interrupt. For an INTID configured as non-maskable, this field is RES0. AU Priority_offset_1B 15 8 15:8 Interrupt priority value from an IMPLEMENTATION DEFINED range, at byte offset 1. Lower priority values correspond to greater priority of the interrupt. For an INTID configured as non-maskable, this field is RES0. AU Priority_offset_0B 7 0 7:0 Interrupt priority value from an IMPLEMENTATION DEFINED range, at byte offset 0. Lower priority values correspond to greater priority of the interrupt. For an INTID configured as non-maskable, this field is RES0. AU For interrupt ID m, when DIV and MOD are the integer division and modulo operations: The corresponding GICR_IPRIORITYR<n> number, n, is given by n = (m-1024) DIV 4. The offset of the required GICR_IPRIORITYR<n>E register is (0x400 + (4*n)). The byte offset of the required Priority field in this register is m MOD 4, where: Byte offset 0 refers to register bits [7:0]. Byte offset 1 refers to register bits [15:8]. Byte offset 2 refers to register bits [23:16]. Byte offset 3 refers to register bits [31:24]. When affinity routing is not enabled for the Security state of an interrupt in GICR_ISACTIVER<n>E, the corresponding bit is RES0. When GICD_CTLR.DS==0: A field that corresponds to a Group 0 or Secure Group 1 interrupt is RAZ/WI to Non-secure accesses. A Non-secure access to a field that corresponds to a Non-secure Group 1 interrupt behaves as described in Software accesses of interrupt priority. Bits corresponding to unimplemented interrupts are RAZ/WI. Implementations must ensure that an interrupt that is pending at the time of the write uses either the old value or the new value and must ensure that the interrupt is neither lost nor handled more than once. The effect of the change must be visible in finite time. 2026-03-26 20:27:25 2026-03_rel