GICR_PROPBASER Redistributor Properties Base Address Register GIC Redistributor RD_base 0x0070 GICR_PROPBASER RW Specifies the base address of the LPI Configuration table, and the Shareability and Cacheability of accesses to the LPI Configuration table. GICR A copy of this register is provided for each Redistributor. An implementation might make this register RO, for example to correspond to an LPI Configuration table in read-only memory. GICR_PROPBASER is a 64-bit register. 63 59 63:59 Reserved, RES0. OuterCache 58 56 58:56 Indicates the Outer Cacheability attributes of accesses to the LPI Configuration table. It is IMPLEMENTATION DEFINED whether this field has a fixed value or can be programmed by software. Implementing this field with a fixed value is deprecated. 0b000 Memory type defined in InnerCache field. For Normal memory, Outer Cacheability is the same as Inner Cacheability. 0b001 Normal Outer Non-cacheable. 0b010 Normal Outer Cacheable Read-allocate, Write-through. 0b011 Normal Outer Cacheable Read-allocate, Write-back. 0b100 Normal Outer Cacheable Write-allocate, Write-through. 0b101 Normal Outer Cacheable Write-allocate, Write-back. 0b110 Normal Outer Cacheable Read-allocate, Write-allocate, Write-through. 0b111 Normal Outer Cacheable Read-allocate, Write-allocate, Write-back. AU 55 52 55:52 Reserved, RES0. Physical_Address 51 12 51:12 Bits [51:12] of the physical address containing the LPI Configuration table. In implementations supporting fewer than 52 bits of physical address, unimplemented upper bits are RES0. AU Shareability 11 10 11:10 Indicates the Shareability attributes of accesses to the LPI Configuration table. It is IMPLEMENTATION DEFINED whether this field has a fixed value or can be programmed by software. Implementing this field with a fixed value is deprecated. 0b00 Non-shareable. 0b01 Inner Shareable. 0b10 Outer Shareable. 0b11 Reserved. Treated as 0b00. AU InnerCache 9 7 9:7 Indicates the Inner Cacheability attributes of accesses to the LPI Configuration table. 0b000 Device-nGnRnE. 0b001 Normal Inner Non-cacheable. 0b010 Normal Inner Cacheable Read-allocate, Write-through. 0b011 Normal Inner Cacheable Read-allocate, Write-back. 0b100 Normal Inner Cacheable Write-allocate, Write-through. 0b101 Normal Inner Cacheable Write-allocate, Write-back. 0b110 Normal Inner Cacheable Read-allocate, Write-allocate, Write-through. 0b111 Normal Inner Cacheable Read-allocate, Write-allocate, Write-back. AU 6 5 6:5 Reserved, RES0. IDbits 4 0 4:0 The number of bits of LPI INTID supported, minus one, by the LPI Configuration table starting at Physical_Address. If the value of this field is larger than the value of GICD_TYPER.IDbits, the GICD_TYPER.IDbits value applies. If the value of this field is less than 0b1101, indicating that the largest INTID is less than 8192 (the smallest LPI interrupt ID), the GIC will behave as if all physical LPIs are out of range. AU It is IMPLEMENTATION DEFINED whether GICR_PROPBASER can be set to different values on different Redistributors. GICR_TYPER.CommonLPIAff identifies the Redistributors that must have GICR_PROPBASER set to the same values whenever GICR_CTLR.EnableLPIs == 1. Setting different values in different copies of GICR_PROPBASER on Redistributors that are required to use a common LPI Configuration table when GICR_CTLR.EnableLPIs == 1 leads to UNPREDICTABLE behavior. Other restrictions apply when a Redistributor caches information from GICR_PROPBASER. For more information, see 'LPI Configuration tables' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069). 2026-03-26 20:27:25 2026-03_rel