GICR_SYNCR Redistributor Synchronize Register GIC Redistributor RD_base 0x00C0 GICR_SYNCR RO Indicates completion of register based invalidate operations. GICR A copy of this register is provided for each Redistributor. GICR_SYNCR is a 32-bit register. 31 1 31:1 Reserved, RES0. Busy 0 0 0 Indicates completion of invalidation operations This field tracks operations initiated on the same Redistributor. 0b0 No operations are in progress. 0b1 A write is in progress to one or more of the following registers: GICR_INVLPIR. GICR_INVALLR. GICv3, GICR_CLRLPIR. When this register is accessed, it is optional that an implementation might wait until all operations are complete before returning a value, in which case GICR_SYNCR.Busy is always 0. This register is mandatory when any of the following are true: GICR_TYPER.Direct is 1. GICR_CTLR.IR is 1. GICv4.1 is implemented. Otherwise, the functionality is IMPLEMENTATION DEFINED. 2026-03-26 20:27:25 2026-03_rel