GICR_WAKER Redistributor Wake Register GIC Redistributor RD_base 0x0014 GICR_WAKER When GICD_CTLR.DS == '1' RW When GICD_CTLR.DS == '0' and an access is Secure RW When GICD_CTLR.DS == '0' and an access is Non-secure RAZ/WI When GICD_CTLR.DS == '0', FEAT_RME is implemented, and an access is Root RW When GICD_CTLR.DS == '0', FEAT_RME is implemented, and an access is Realm RAZ/WI Permits software to control the behavior of the WakeRequest power management signal corresponding to the Redistributor. Power management operations follow the rules in 'Power management' in in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069). GICR A copy of this register is provided for each Redistributor. GICR_WAKER is a 32-bit register. IMPLEMENTATION DEFINED 31 31 31 IMPLEMENTATION DEFINED. 30 3 30:3 Reserved, RES0. ChildrenAsleep 2 2 2 Read-only. Indicates whether the connected PE is quiescent: 0b0 An interface to the connected PE might be active. 0b1 All interfaces to the connected PE are quiescent. '1' ProcessorSleep 1 1 1 Indicates whether the Redistributor can assert the WakeRequest signal: Before powering down a PE, software must set this bit to 1 and wait until ChildrenAsleep == 1. After powering up a PE, or following a failed powerdown, software must set this bit to 0 and wait until ChildrenAsleep == 0.Changing ProcessorSleep from 1 to 0 when ChildrenAsleep is not 1 results in UNPREDICTABLE behavior. Changing ProcessorSleep from 0 to 1 when the Enable for each interrupt group in the associated CPU interface is not 0 results in UNPREDICTABLE behavior. 0b0 This PE is not in, and is not entering, a low power state. 0b1 The PE is either in, or is in the process of entering, a low power state. All interrupts that arrive at the Redistributor: Assert a WakeRequest signal. Are held in the pending state at the Redistributor, and are not communicated to the CPU interface. When ProcessorSleep == 1, the Redistributor must ensure that any interrupts that are pending on the CPU interface are released.For an implementation that is using the GIC Stream Protocol Interface: A Quiesce command puts the interface between the Redistributor and the CPU interface in a quiescent state. For more information, see 'Quiesce (IRI)' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069). A Release command releases any interrupts that are pending on the CPU interface. For more information, see 'Release (ICC)' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069). '1' IMPLEMENTATION DEFINED 0 0 0 IMPLEMENTATION DEFINED. To ensure a Redistributor is quiescent, software must write to GICR_WAKER with ProcessorSleep == 1, then poll the register until ChildrenAsleep == 1. Resetting the connected PE when GICR_WAKER.ProcessorSleep==0 or GICR_WAKER.ChildrenAsleep==0, can lead to UNPREDICTABLE behavior in the IRI. Resetting the IRI when GICR_WAKER.ProcessorSleep==0 or GICR_WAKER.ChildrenAsleep==0 can lead to UNPREDICTABLE behavior in the connected PE. 2026-03-26 20:27:25 2026-03_rel