GICV_APR<n> Virtual Machine Active Priorities Registers when FEAT_GICv3_LEGACY is implemented and EL2 is implemented 0 3 GIC Virtual CPU interface 0x00D0 + (4 * n) GICV_APR<n> When GICD_CTLR.DS == '0' RW When an access is Secure RW When an access is Non-secure RW Provides information about interrupt active priorities. These registers correspond to the physical CPU interface registers GICC_APR<n>. GICV When System register access is disabled for EL2, these registers access GICH_APR<n>, and all active priorities for virtual machines are held in GICH_APR<n> regardless of interrupt group. When System register access is enabled for EL2, these registers access ICH_AP1R<n>_EL2, and all active priorities for virtual machines are held in ICH_AP1R<n>_EL2 regardless of interrupt group. GICV_APR<n> is a 32-bit register. P<x> 31 0 31:0 Provides information about active priorities for the virtual machine. See GICH_APR<n> and ICH_AP1R<n>_EL2 for the correspondence between priorities and bits. 31 0 If System register access is not enabled for EL2, these registers access GICH_APR<n>. If System register access is enabled for EL2, these registers access ICH_AP1R<n>_EL2. All active priority mapped guests are held in the accessed registers, regardless of interrupt group. 2026-03-26 20:27:25 2026-03_rel