GICV_CTLR Virtual Machine Control Register when FEAT_GICv3_LEGACY is implemented and EL2 is implemented GIC Virtual CPU interface 0x0000 GICV_CTLR When GICD_CTLR.DS == '0' RW When an access is Secure RW When an access is Non-secure RW Controls the behavior of virtual interrupts. This register corresponds to the physical CPU interface register GICC_CTLR. GICV This register is available when a GIC implementation supports interrupt virtualization. GICV_CTLR is a 32-bit register. 31 10 31:10 Reserved, RES0. EOImode 9 9 9 Controls the behavior associated with the GICV_EOIR, GICV_AEOIR, and GICV_DIR registers: 0b0 Writes to GICV_EOIR and GICV_AEOIR perform priority drop and deactivate interrupt operations simultaneously. Behavior on a write to GICV_DIR is unpredictable. When it has completed processing the interrupt, the virtual machine writes to GICV_EOIR or GICV_AEOIR to deactivate the interrupt. The write updates the List registers and causes the virtual CPU interface to signal the interrupt completion to the physical Distributor. 0b1 Writes to GICV_EOIR and GICV_AEOIR perform priority drop operation only. Writes to GICV_DIR perform deactivate interrupt operation only. When it has completed processing the interrupt, the virtual machine writes to GICV_DIR to deactivate the interrupt. The write updates the List registers and causes the virtual CPU interface to signal the interrupt completion to the Distributor. AU 8 5 8:5 Reserved, RES0. CBPR 4 4 4 Controls whether GICV_BPR affects both Group 0 and Group 1 interrupts: For more information, see 'Priority grouping' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069). 0b0 GICV_BPR affects Group 0 virtual interrupts only. GICV_ABPR affects Group 1 virtual interrupts only. 0b1 GICV_BPR affects both Group 0 and Group 1 virtual interrupts. AU FIQEn 3 3 3 FIQ Enable. Controls whether Group 0 virtual interrupts are presented as virtual FIQs: 0b0 Group 0 virtual interrupts are presented as virtual IRQs. 0b1 Group 0 virtual interrupts are presented as virtual FIQs. AU AckCtl 2 2 2 Arm deprecates use of this bit. Arm strongly recommends that software is written to operate with this bit always cleared to 0. Acknowledge control. When the highest priority interrupt is Group 1, determines whether GICV_IAR causes the CPU interface to acknowledge the interrupt or returns the spurious identifier 1022, and whether GICV_HPPIR returns the interrupt ID or the special identifier 1022. 0b0 If the highest priority pending interrupt is Group 1, a read of GICV_IAR or GICV_HPPIR returns an interrupt ID of 1022. 0b1 If the highest priority pending interrupt is Group 1, a read of GICV_IAR or GICV_HPPIR returns the interrupt ID of the corresponding interrupt. AU EnableGrp1 1 1 1 Enables the signaling of Group 1 virtual interrupts by the virtual CPU interface to the virtual machine: 0b0 Signaling of Group 1 interrupts is disabled. 0b1 Signaling of Group 1 interrupts is enabled. AU EnableGrp0 0 0 0 Enables the signaling of Group 0 virtual interrupts by the virtual CPU interface to the virtual machine: 0b0 Signaling of Group 0 interrupts is disabled. 0b1 Signaling of Group 0 interrupts is enabled. AU This register is used only when System register access is not enabled. When System register access is enabled: For AArch32 implementations, ICC_CTLR provides equivalent functionality. For AArch64 implementations, ICC_CTLR_EL1 provides equivalent functionality. 2026-03-26 20:27:25 2026-03_rel