GICV_DIR Virtual Machine Deactivate Interrupt Register when FEAT_GICv3_LEGACY is implemented and EL2 is implemented GIC Virtual CPU interface 0x1000 GICV_DIR When GICD_CTLR.DS == '0' WO When an access is Secure WO When an access is Non-secure WO Deactivates a specified virtual interrupt in the GICH_LR<n> List registers. This register corresponds to the physical CPU interface register GICC_DIR. GICV This register is available when the GIC implementation supports interrupt virtualization. GICV_DIR is a 32-bit register. 31 25 31:25 Reserved, RES0. INTID 24 0 24:0 The INTID of the signaled interrupt. INTIDs 1020-1023 are reserved and convey additional information such as spurious interrupts.When affinity routing is not enabled: Bits [23:13] are RES0. For SGIs, bits [12:10] identify the CPU interface corresponding to the source PE. For all other interrupts these bits are RES0. When the virtual machine writes to this register, the specified interrupt in the List registers is changed from active to inactive, or from active and pending to pending. If the specified interrupt is present in the List registers but is not in either the active or active and pending states, the effect is UNPREDICTABLE. If the specified interrupt is not present in the List registers, GICH_HCR.EOICount is incremented, potentially generating a maintenance interrupt. If the specified interrupt is not present in the List registers, the virtual machine cannot recover the INTID. Therefore, the hypervisor must ensure that, when GICV_CTLR.EOImode == 1, no more than one active interrupt is transferred from the List registers into a software list. If more than one active interrupt that is not stored in the List registers exists, the hypervisor must handle accesses to GICV_DIR in software, typically by trapping these accesses.If the corresponding GICH_LR<n>.HW == 1, indicating a hardware interrupt, then a deactivate request is sent to the physical Distributor, identifying the physical INTID from the corresponding field in the List register. This effect is identical to a Non-secure write to GICC_DIR from the PE having that physical INTID. This means that if the corresponding physical interrupt is marked as Group 0, the request is ignored. Interrupt deactivation using this register is based on the provided INTID, with no requirement to deactivate interrupts in any particular order. A single register is therefore used to deactivate both Group 0 and Group 1 interrupts. This register is used only when System register access is not enabled. When System register access is enabled: For AArch32 implementations, ICC_DIR provides equivalent functionality. For AArch64 implementations, ICC_DIR_EL1 provides equivalent functionality. Writes to this register are valid only when GICV_CTLR.EOImode == 1. Writes to this register are otherwise UNPREDICTABLE. When affinity routing is enabled, it is a programming error to use memory-mapped registers to access the GIC. 2026-03-26 20:27:25 2026-03_rel