GICV_HPPIR
Virtual Machine Highest Priority Pending Interrupt Register
when FEAT_GICv3_LEGACY is implemented and EL2 is implemented
GIC Virtual CPU interface
0x0018
GICV_HPPIR
When GICD_CTLR.DS == '0'
RO
When an access is Secure
RO
When an access is Non-secure
RO
Provides the INTID of the highest priority pending Group 0 virtual interrupt in the List registers.
This register corresponds to the physical CPU interface register GICC_HPPIR.
GICV
This register is available when the GIC implementation supports interrupt virtualization.
GICV_HPPIR is a 32-bit register.
31
25
31:25
Reserved, RES0.
INTID
24
0
24:0
The INTID of the signaled interrupt.
INTIDs 1020-1023 are reserved and convey additional information such as spurious interrupts.When affinity routing is not enabled:
Bits [23:13] are RES0.
For SGIs, bits [12:10] identify the CPU interface corresponding to the source PE. For all other interrupts these bits are RES0.
Reads of the GICC_HPPIR that do not return a valid INTID return a spurious INTID, 1022 or 1023. See 'Special INTIDs' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069).
Highest priority pending interrupt GroupGICV_HPPIR readGICV_CTLR.AckCtlReturned INTID
1Non-securexID of Group 1 interrupt
1Secure01022
1Secure1ID of Group 1 interrupt
0Non-securex1023
0SecurexID of Group 0 interrupt
No pending interruptsxx1023
If the CPU interface supports only a single Security state, the entries that apply to Secure reads describe the behavior.
This register is used only when System register access is not enabled. When System register access is enabled:
For AArch32 implementations, ICC_HPPIR0 provides equivalent functionality.
For AArch64 implementations, ICC_HPPIR0_EL1 provides equivalent functionality.
This register is used for Group 0 interrupts only. GICV_AHPPIR provides equivalent functionality for Group 1 interrupts.
When affinity routing is enabled, it is a programming error to use memory-mapped registers to access the GIC.
2026-03-26 20:27:25
2026-03_rel