GICV_IAR Virtual Machine Interrupt Acknowledge Register when FEAT_GICv3_LEGACY is implemented and EL2 is implemented GIC Virtual CPU interface 0x000C GICV_IAR When GICD_CTLR.DS == '0' RO When an access is Secure RO When an access is Non-secure RO Provides the INTID of the signaled Group 0 virtual interrupt. A read of this register by the PE acts as an acknowledge for the interrupt. This register corresponds to the physical CPU interface register GICC_IAR. GICV This register is available when the GIC implementation supports interrupt virtualization. GICV_IAR is a 32-bit register. 31 25 31:25 Reserved, RES0. INTID 24 0 24:0 The INTID of the signaled interrupt. INTIDs 1020-1023 are reserved and convey additional information such as spurious interrupts.When affinity routing is not enabled: Bits [23:13] are RES0. For SGIs, bits [12:10] identify the CPU interface corresponding to the source PE. For all other interrupts these bits are RES0. When the virtual machine writes to this register, the virtual CPU interface acknowledges the highest priority pending virtual interrupt and sets the state in the corresponding List register to active. The appropriate bit in the active priorities register GICH_APR<n> is set to 1. If GICH_LR<n>.HW == 0, indicating that the interrupt is software-triggered, then bits [12:10] of GICH_LR<n> are returned in bits [12:10] of GICV_IAR. Otherwise bits [12:10] are RES0. A read of this register returns the spurious INTID 1023 if either of the following is true: There are no pending interrupts of sufficiently high priority value to be signaled to the PE with the virtual CPU interface enabled and GICH_HCR.En == 1. Interrupt signaling by the virtual CPU interface is disabled. A read of this register returns the spurious INTID 1022 if the highest priority pending interrupt is Group 1 and GICV_CTLR.AckCtl == 0. This register is used only when System register access is not enabled. When System register access is enabled: For AArch32 implementations, ICC_IAR0 provides equivalent functionality. For AArch64 implementations, ICC_IAR0_EL1 provides equivalent functionality. This register is used for Group 0 interrupts only. GICV_AIAR provides equivalent functionality for Group 1 interrupts. When affinity routing is enabled, it is a programming error to use memory-mapped registers to access the GIC. 2026-03-26 20:27:25 2026-03_rel