GICV_PMR Virtual Machine Priority Mask Register when FEAT_GICv3_LEGACY is implemented and EL2 is implemented GIC Virtual CPU interface 0x0004 GICV_PMR When GICD_CTLR.DS == '0' RW When an access is Secure RW When an access is Non-secure RW This register provides a virtual interrupt priority filter. Only virtual interrupts with a higher priority than the value in this register are signaled to the PE. Higher interrupt priority corresponds to a lower value of the Priority field. This register corresponds to the physical CPU interface register GICC_PMR. GICV This register is available when the GIC implementation supports interrupt virtualization. The Priority field of this register is aliased to GICH_VMCR.VMPR, to enable state to be switched easily between virtual machines during context-switching. GICV_PMR is a 32-bit register. 31 8 31:8 Reserved, RES0. Priority 7 0 7:0 The priority mask level for the virtual CPU interface. If the priority of the interrupt is higher than the value indicated by this field, the interface signals the interrupt to the PE. If the GIC implementation supports fewer than 256 priority levels some bits might be RAZ/WI, as follows: For 128 supported levels, bit [0] = 0b0. For 64 supported levels, bits [1:0] = 0b00. For 32 supported levels, bits [2:0] = 0b000. For 16 supported levels, bits [3:0] = 0b0000. For more information, see 'Interrupt prioritization' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069). AU This register is used only when System register access is not enabled. When System register access is enabled: For AArch32 implementations, ICC_PMR provides equivalent functionality. For AArch64 implementations, ICC_PMR_EL1 provides equivalent functionality. 2026-03-26 20:27:25 2026-03_rel