GICV_STATUSR Virtual Machine Error Reporting Status Register when FEAT_GICv3_LEGACY is implemented and EL2 is implemented GIC Virtual CPU interface 0x002C GICV_STATUSR When GICD_CTLR.DS == '0' RW When an access is Secure RW When an access is Non-secure RW Provides software with a mechanism to detect: Accesses to reserved locations. Writes to read-only locations. Reads of write-only locations. GICV In systems where this register is implemented, Arm expects that when a virtual machine is scheduled, the hypervisor ensures that this register is cleared to 0. The hypervisor might check for illegal accesses when the virtual machine is unscheduled. GICV_STATUSR is a 32-bit register. 31 4 31:4 Reserved, RES0. WROD 3 3 3 Write to an RO location. When a violation is detected, software must write 1 to this register to reset it. 0b0 Normal operation. 0b1 A write to an RO location has been detected. RWOD 2 2 2 Read of a WO location. When a violation is detected, software must write 1 to this register to reset it. 0b0 Normal operation. 0b1 A read of a WO location has been detected. WRD 1 1 1 Write to a reserved location. When a violation is detected, software must write 1 to this register to reset it. 0b0 Normal operation. 0b1 A write to a reserved location has been detected. RRD 0 0 0 Read of a reserved location. When a violation is detected, software must write 1 to this register to reset it. 0b0 Normal operation. 0b1 A read of a reserved location has been detected. This is an optional register. If the register is implemented, GICC_STATUSR must also be implemented. If the register is not implemented, the location is RAZ/WI. This register is used only when System register access is not enabled. If System register access is enabled, this register is not updated. Equivalent function might be provided by appropriate traps and exceptions. 2026-03-26 20:27:25 2026-03_rel