GITS_BASER<n> ITS Table Descriptors 0 7 GIC ITS control 0x0100 + (8 * n) GITS_BASER<n> RW Specifies the base address and size of the ITS tables. GITS A copy of this register is provided for each ITS table. Bits [63:32] and bits [31:0] are accessible independently. A maximum of 8 GITS_BASER<n> registers can be provided. Unimplemented registers are RES0. When GITS_CTLR.Enabled == 1 or GITS_CTLR.Quiescent == 0, writing this register is UNPREDICTABLE. GITS_BASER<n> is a 64-bit register. Valid 63 63 63 Indicates whether software has allocated memory for the table: 0b0 No memory is allocated for the table. The ITS discards any writes to the interrupt translation page when either: GITS_BASER<n>.Type specifies any valid table entry type other than interrupt collections, that is, any value other than 0b100. GITS_BASER<n>.Type specifies an interrupt collection and GITS_TYPER.HCC == 0. 0b1 Memory is allocated to the table. '0' Indirect 62 62 62 This field indicates whether an implemented register specifies a single, flat table or a two-level table where the first level contains a list of descriptors. For more information, see 'The ITS tables' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069). This field is RAZ/WI for GIC implementations that only support flat tables. If the maximum width of the scaling factor that is identified by GITS_BASER<n>.Type and the smallest page size that is supported result in a single level table that requires multiple pages, then implementing this bit as RAZ/WI is DEPRECATED. 0b0 Single Level. The Size field indicates the number of pages used by the ITS to store data associated with each table entry. 0b1 Two Level. The Size field indicates the number of pages which contain an array of 64-bit descriptors to pages that are used to store the data associated with each table entry. A little endian memory order model is used. AU InnerCache 61 59 61:59 Indicates the Inner Cacheability attributes of accesses to the table. The possible values of this field are: 0b000 Device-nGnRnE. 0b001 Normal Inner Non-cacheable. 0b010 Normal Inner Cacheable Read-allocate, Write-through. 0b011 Normal Inner Cacheable Read-allocate, Write-back. 0b100 Normal Inner Cacheable Write-allocate, Write-through. 0b101 Normal Inner Cacheable Write-allocate, Write-back. 0b110 Normal Inner Cacheable Read-allocate, Write-allocate, Write-through. 0b111 Normal Inner Cacheable Read-allocate, Write-allocate, Write-back. AU Type 58 56 58:56 Read only. Specifies the type of entity that requires entries in the corresponding table. The possible values of the field are: Other values are reserved. For FEAT_GICv4p1, the registers are allocated as follows: GITS_BASER0.Type is 0b001 (Device). GITS_BASER1.Type is either 0b100 (Collection Table) or 0b000 (Unimplemented). GITS_BASER2.Type is either 0b010 (vPE) or 0b000 (Unimplemented). GITS_BASER<n>.Type, where 'n' is in the range 3 to 7, is 0b000 (Unimplemented). For FEAT_GICv3, FEAT_GICv3p1, and FEAT_GICv4, Arm recommends that the GITS_BASER<n> use the same allocations. Other allocations of Type values are deprecated. 0b000 Unimplemented. This register does not correspond to an ITS table. 0b001 Devices. This register corresponds to an ITS table that scales with the width of the DeviceID. Only a single GITS_BASER<n> register reports this type. 0b010 vPEs. FEAT_GICv4 only. This register corresponds to an ITS table that scales with the number of vPEs in the system. The table requires (ENTRY_SIZE * N) bytes of memory, where N is the number of vPEs in the system. Only a single GITS_BASER<n> register reports this type. 0b100 Interrupt collections. This register corresponds to an ITS table that scales with the number of interrupt collections in the system. The table requires (ENTRY_SIZE * N) bytes of memory, where N is the number of interrupt collections. Not more than one GITS_BASER<n> register will report this type. OuterCache 55 53 55:53 Indicates the Outer Cacheability attributes of accesses to the table. The possible values of this field are: It is IMPLEMENTATION DEFINED whether this field has a fixed value or can be programmed by software. Implementing this field with a fixed value is deprecated. 0b000 Memory type defined in InnerCache field. For Normal memory, Outer Cacheability is the same as Inner Cacheability. 0b001 Normal Outer Non-cacheable. 0b010 Normal Outer Cacheable Read-allocate, Write-through. 0b011 Normal Outer Cacheable Read-allocate, Write-back. 0b100 Normal Outer Cacheable Write-allocate, Write-through. 0b101 Normal Outer Cacheable Write-allocate, Write-back. 0b110 Normal Outer Cacheable Read-allocate, Write-allocate, Write-through. 0b111 Normal Outer Cacheable Read-allocate, Write-allocate, Write-back. AU Entry_Size 52 48 52:48 Read-only. Specifies the number of bytes per table entry, minus one. Physical_Address 47 12 47:12 Physical Address. When Page_Size is 4KB or 16KB: Bits [51:48] of the base physical address are zero. This field provides bits[47:12] of the base physical address of the table. Bits[11:0] of the base physical address are zero. The address must be aligned to the size specified in the Page Size field. Otherwise the effect is CONSTRAINED UNPREDICTABLE, and can be one of the following: Bits[X:12], where X is derived from the page size, are treated as zero. The value of bits[X:12] are used when calculating the address of a table access. When Page_Size is 64KB: Bits[47:16] of the register provide bits[47:16] of the base physical address of the table. Bits[15:12] of the register provide bits[51:48] of the base physical address of the table. Bits[15:0] of the base physical address are 0. In implementations that support fewer than 52 bits of physical address, any unimplemented upper bits might be RAZ/WI. AU Shareability 11 10 11:10 Indicates the Shareability attributes of accesses to the table. The possible values of this field are: It is IMPLEMENTATION DEFINED whether this field has a fixed value or can be programmed by software. Implementing this field with a fixed value is deprecated. 0b00 Non-shareable. 0b01 Inner Shareable. 0b10 Outer Shareable. 0b11 Reserved. Treated as 0b00. AU Page_Size 9 8 9:8 The size of page that the table uses: If the GIC implementation supports only a single, fixed page size, this field might be RO. 0b00 4KB. 0b01 16KB. 0b10 64KB. 0b11 Reserved. Treated as 0b10. AU Size 7 0 7:0 The number of pages of physical memory allocated to the table, minus one. GITS_BASER<n>.Page_Size specifies the size of each page. If GITS_BASER<n>.Type == 0, this field is RAZ/WI. AU 2026-03-26 20:27:25 2026-03_rel