MIDR_EL1 Main ID Register The power domain of MIDR_EL1 is IMPLEMENTATION DEFINED Debug 0xD00 MIDR_EL1 When DoubleLockStatus() or !IsCorePowered() IMPDEF RO MIDR_EL1 Architectural AArch64 31 0 31 0 31 0 31 0 MIDR Architectural AArch32 31 0 31 0 31 0 31 0 Provides identification information for the PE, including an implementer code for the device and a device ID number. Identification Registers MIDR_EL1 is a 32-bit register. Implementer 31 24 31:24 The Implementer code. This field must hold an implementer code that has been assigned by Arm. Arm can assign codes that are not published in this manual. All values not assigned by Arm are reserved and must not be used. 0x00 Reserved for software use. 0x41 Arm Limited. 0x42 Broadcom Corporation. 0x43 Cavium Inc. 0x44 Digital Equipment Corporation. 0x46 Fujitsu Ltd. 0x49 Infineon Technologies AG. 0x4D Motorola or Freescale Semiconductor Inc. 0x4E NVIDIA Corporation. 0x50 Applied Micro Circuits Corporation. 0x51 Qualcomm Inc. 0x56 Marvell International Ltd. 0x69 Intel Corporation. 0xC0 Ampere Computing. RO Variant 23 20 23:20 Variant number. Typically, this field is used to distinguish between different product variants, or major revisions of a product. This field has an IMPLEMENTATION DEFINED value. RO Architecture 19 16 19:16 Architecture version. All other values are reserved. 0b0001 Armv4. 0b0010 Armv4T. 0b0011 Armv5 (obsolete). 0b0100 Armv5T. 0b0101 Armv5TE. 0b0110 Armv5TEJ. 0b0111 Armv6. 0b1111 Architectural features are individually identified in the ID_* registers. RO PartNum 15 4 15:4 Primary Part Number for the device. On processors implemented by Arm, if the top four bits of the primary part number are 0x0 or 0x7, the variant and architecture are encoded differently. This field has an IMPLEMENTATION DEFINED value. RO Revision 3 0 3:0 Revision number for the device. This field has an IMPLEMENTATION DEFINED value. RO 2026-03-26 20:27:25 2026-03_rel