<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
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<?xml-stylesheet href="one_register.xsl" type="text/xsl" ?>







<register_page>
  <registers>
  
    <register is_register="True" is_internal="False" is_stub_entry="False">
      <reg_short_name>MPAMCFG_IN_TL</reg_short_name>
        
        <reg_long_name>MPAM Ingress PARTID Translation Configuration Register</reg_long_name>

        <power_domain_text>The power domain of MPAMCFG_IN_TL is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word></power_domain_text>


      
            <reg_condition otherwise="RES0">when FEAT_MPAM_MSC_DOMAINS is implemented and MPAMF_IDR.HAS_IN_TL == '1'</reg_condition>
      

    
  <reg_address
      external_access="False"
    mem_map_access="True"
      power_domain="None"
  >
    <reg_component>MPAM</reg_component>
    <reg_frame>MPAMF_BASE_s</reg_frame>
    <reg_offset><hexnumber>0x3008</hexnumber></reg_offset>
    <reg_instance>MPAMCFG_IN_TL_s</reg_instance>
    <reg_access>
      
        
      <reg_access_state>
          <reg_access_level>When FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented</reg_access_level>
          <reg_access_type>RW</reg_access_type>
      </reg_access_state>
    </reg_access>
</reg_address>
    
  <reg_address
      external_access="False"
    mem_map_access="True"
      power_domain="None"
  >
    <reg_component>MPAM</reg_component>
    <reg_frame>MPAMF_BASE_ns</reg_frame>
    <reg_offset><hexnumber>0x3008</hexnumber></reg_offset>
    <reg_instance>MPAMCFG_IN_TL_ns</reg_instance>
    <reg_access>
      
        
      <reg_access_state>
          <reg_access_level>When FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented</reg_access_level>
          <reg_access_type>RW</reg_access_type>
      </reg_access_state>
    </reg_access>
</reg_address>
    
  <reg_address
      external_access="False"
    mem_map_access="True"
      power_domain="None"
  >
    <reg_component>MPAM</reg_component>
    <reg_frame>MPAMF_BASE_rt</reg_frame>
    <reg_offset><hexnumber>0x3008</hexnumber></reg_offset>
    <reg_instance>MPAMCFG_IN_TL_rt</reg_instance>
    <reg_access>
      
        
      <reg_access_state>
          <reg_access_level>When FEAT_RME is implemented and (FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented)</reg_access_level>
          <reg_access_type>RW</reg_access_type>
      </reg_access_state>
    </reg_access>
</reg_address>
    
  <reg_address
      external_access="False"
    mem_map_access="True"
      power_domain="None"
  >
    <reg_component>MPAM</reg_component>
    <reg_frame>MPAMF_BASE_rl</reg_frame>
    <reg_offset><hexnumber>0x3008</hexnumber></reg_offset>
    <reg_instance>MPAMCFG_IN_TL_rl</reg_instance>
    <reg_access>
      
        
      <reg_access_state>
          <reg_access_level>When FEAT_RME is implemented and (FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented)</reg_access_level>
          <reg_access_type>RW</reg_access_type>
      </reg_access_state>
    </reg_access>
</reg_address>



          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        




      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>Enables ingress PARTID translation and configures direct ingress PARTID translations.</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
          <reg_group>MPAM</reg_group>
      </reg_groups>
      <reg_configuration>
        
    
      <configuration_text>
        <para>The power and reset domain of each MSC component is specific to that component.</para>
      </configuration_text>

      </reg_configuration>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>MPAMCFG_IN_TL is a 32-bit register.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="32">
  <text_before_fields/>
  <field id="fieldset_0-31_31" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>ENABLE</field_name>
    <field_msb>31</field_msb>
    <field_lsb>31</field_lsb>
    <rel_range>31</rel_range>
    <field_description order="before">
      <para>Enables ingress PARTID translation in the MSC.</para>
    </field_description>
    <field_values impdef="False">
      <field_value_instance>
        <field_value>0b0</field_value>
        <field_value_description>
          <para>Ingress PARTID translation is disabled.</para>
        </field_value_description>
      </field_value_instance>
      <field_value_instance>
        <field_value>0b1</field_value>
        <field_value_description>
          <para>Ingress PARTID translation is enabled.</para>
        </field_value_description>
      </field_value_instance>
    </field_values>
  </field>
  <field id="fieldset_0-30_16" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>30</field_msb>
    <field_lsb>16</field_lsb>
    <rel_range>30:16</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
  </field>
  <field id="fieldset_0-15_0-1" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" reserved_type="RES0">
    <field_name>PARTID_TL</field_name>
    <field_msb>15</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>15:0</rel_range>
    <field_description order="before">
      <para>PARTID to be used as direct translation of the ingress PARTID configured in <register_link state="ext" id="ext-mpamcfg_part_sel.xml">MPAMCFG_PART_SEL</register_link>.PARTID_SEL when <register_link state="ext" id="ext-mpamcfg_part_sel.xml">MPAMCFG_PART_SEL</register_link>.INGRESS_TL == 1.</para>
    </field_description>
    <fields_condition>When MPAMF_IN_TL_IDR.HAS_DIRECT_TL == '1'</fields_condition>
  </field>
  <field id="fieldset_0-15_0-2" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>15</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>15:0</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
    <fields_condition>Otherwise</fields_condition>
  </field>
  <text_after_fields/>
</fields>




<reg_fieldset length="32">
  <fieldat id="fieldset_0-31_31" msb="31" lsb="31"/>
  <fieldat id="fieldset_0-30_16" msb="30" lsb="16"/>
  <fieldat id="fieldset_0-15_0-1" msb="15" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>

      <access_mechanisms>
          


  
    
      <access_permission_text>
        <para>If both <xref linkend="#FEAT_MPAM">FEAT_MPAM</xref> and <xref linkend="#FEAT_RME">FEAT_RME</xref> are implemented, the following statements apply:</para>

      </access_permission_text>
      <access_permission_text>
        <list type="unordered">
<listitem><content>
<para>In a system that supports Secure, Non-secure, Root, and Realm memory maps, there must be MPAM feature pages in all four address maps:</para>
</content>
</listitem><listitem><content>
<para>MPAMCFG_IN_TL_s must only be accessible from the Secure MPAM feature page.</para>
</content>
</listitem><listitem><content>
<para>MPAMCFG_IN_TL_ns must only be accessible from the Non-secure MPAM feature page.</para>
</content>
</listitem><listitem><content>
<para>MPAMCFG_IN_TL_rt must only be accessible from the Root MPAM feature page.</para>
</content>
</listitem><listitem><content>
<para>MPAMCFG_IN_TL_rl must only be accessible from the Realm MPAM feature page.</para>
</content>
</listitem><listitem><content>
<para>MPAMCFG_IN_TL_s, MPAMCFG_IN_TL_ns, MPAMCFG_IN_TL_rt, and MPAMCFG_IN_TL_rl must be separate registers:</para>
</content>
</listitem><listitem><content>
<para>The Secure instance (MPAMCFG_IN_TL_s) accesses the ingress PARTID translation used for Secure PARTIDs.</para>
</content>
</listitem><listitem><content>
<para>The Non-secure instance (MPAMCFG_IN_TL_ns) accesses the ingress PARTID translation used for Non-secure PARTIDs.</para>
</content>
</listitem><listitem><content>
<para>The Root instance (MPAMCFG_IN_TL_rt) accesses the ingress PARTID translation used for Root PARTIDs.</para>
</content>
</listitem><listitem><content>
<para>The Realm instance (MPAMCFG_IN_TL_rl) accesses the ingress PARTID translation used for Realm PARTIDs.</para>
</content>
</listitem></list>

      </access_permission_text>
      <access_permission_text>
        <para>When RIS is implemented, loads and stores to MPAMCFG_IN_TL access the ingress PARTID translation configuration settings without being affected by <register_link state="ext" id="ext-mpamcfg_part_sel.xml">MPAMCFG_PART_SEL</register_link>.RIS.</para>
      </access_permission_text>





    
    
    
    

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>