<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
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<register_page>
  <registers>
  
    <register is_register="True" is_internal="False" is_stub_entry="False">
      <reg_short_name>MPAMCFG_MBW_PBM&lt;n&gt;</reg_short_name>
        
        <reg_long_name>MPAM Bandwidth Portion Bitmap Partition Configuration Register</reg_long_name>

        <power_domain_text>The power domain of MPAMCFG_MBW_PBM&lt;n&gt; is <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word></power_domain_text>


      
            <reg_condition otherwise="RES0">when (FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p0 is implemented), MPAMF_IDR.HAS_MBW_PART == '1', and MPAMF_MBW_IDR.HAS_PBM == '1'</reg_condition>
          <reg_array>
              <reg_array_start>0</reg_array_start>
              <reg_array_end>127</reg_array_end>
         </reg_array>
      

    
  <reg_address
      external_access="False"
    mem_map_access="True"
      power_domain="None"
  >
    <reg_component>MPAM</reg_component>
    <reg_frame>MPAMF_BASE_s</reg_frame>
    <reg_offset><hexnumber>0x2000</hexnumber> + (4 * n)</reg_offset>
    <reg_instance>MPAMCFG_MBW_PBM&lt;n&gt;_s</reg_instance>
    <reg_access>
      
        
      <reg_access_state>
          <reg_access_level>When FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented</reg_access_level>
          <reg_access_type>RW</reg_access_type>
      </reg_access_state>
    </reg_access>
</reg_address>
    
  <reg_address
      external_access="False"
    mem_map_access="True"
      power_domain="None"
  >
    <reg_component>MPAM</reg_component>
    <reg_frame>MPAMF_BASE_ns</reg_frame>
    <reg_offset><hexnumber>0x2000</hexnumber> + (4 * n)</reg_offset>
    <reg_instance>MPAMCFG_MBW_PBM&lt;n&gt;_ns</reg_instance>
    <reg_access>
      
        
      <reg_access_state>
          <reg_access_level>When FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented</reg_access_level>
          <reg_access_type>RW</reg_access_type>
      </reg_access_state>
    </reg_access>
</reg_address>
    
  <reg_address
      external_access="False"
    mem_map_access="True"
      power_domain="None"
  >
    <reg_component>MPAM</reg_component>
    <reg_frame>MPAMF_BASE_rt</reg_frame>
    <reg_offset><hexnumber>0x2000</hexnumber> + (4 * n)</reg_offset>
    <reg_instance>MPAMCFG_MBW_PBM&lt;n&gt;_rt</reg_instance>
    <reg_access>
      
        
      <reg_access_state>
          <reg_access_level>When FEAT_RME is implemented and (FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p0 is implemented)</reg_access_level>
          <reg_access_type>RW</reg_access_type>
      </reg_access_state>
    </reg_access>
</reg_address>
    
  <reg_address
      external_access="False"
    mem_map_access="True"
      power_domain="None"
  >
    <reg_component>MPAM</reg_component>
    <reg_frame>MPAMF_BASE_rl</reg_frame>
    <reg_offset><hexnumber>0x2000</hexnumber> + (4 * n)</reg_offset>
    <reg_instance>MPAMCFG_MBW_PBM&lt;n&gt;_rl</reg_instance>
    <reg_access>
      
        
      <reg_access_state>
          <reg_access_level>When FEAT_RME is implemented and (FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p0 is implemented)</reg_access_level>
          <reg_access_type>RW</reg_access_type>
      </reg_access_state>
    </reg_access>
</reg_address>



          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        




      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>The MPAMCFG_MBW_PBM&lt;n&gt; register array gives access to the memory bandwidth portion bitmap. Each register in the array is a read/write register that configures whether a PARTID is allowed to allocate bandwidth portions within a range.</para>

      </purpose_text>
      <purpose_text>
        <para>The range of portions covered in MPAMCFG_MBW_PBM&lt;n&gt; is from portion &lt;32*n&gt; to portion &lt;32*n +31&gt;.</para>

      </purpose_text>
      <purpose_text>
        <para>After setting <register_link state="ext" id="ext-mpamcfg_part_sel.xml">MPAMCFG_PART_SEL</register_link> with a PARTID, software writes to one or more of the MPAMCFG_MBW_PBM&lt;n&gt; registers to configure with bandwidth portions the PARTID is allowed to allocate.</para>

      </purpose_text>
      <purpose_text>
        <para>The MPAMCFG_MBW_PBM&lt;n&gt; register that contains the bitmap bit corresponding to memory bandwidth portion p has n equal to p[11:5]. The field, P&lt;x&gt; of that MPAMCFG_MBW_PBM&lt;n&gt; register that contains the bitmap bit corresponding to memory bandwidth portion p has &lt;x&gt; equal to p[4:0].</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
          <reg_group>MPAM</reg_group>
      </reg_groups>
      <reg_configuration>
        
    
      <configuration_text>
        <para>If <register_link state="ext" id="ext-mpamf_idr.xml">MPAMF_IDR</register_link>.HAS_RIS is 1, the control settings accessed are those of the resource instance currently selected by <register_link state="ext" id="ext-mpamcfg_part_sel.xml">MPAMCFG_PART_SEL</register_link>.RIS and the PARTID selected by MPAMCFG_PART_SEL.PARTID_SEL.</para>

      </configuration_text>
      <configuration_text>
        <para>If <xref linkend="#FEAT_MPAMv0p1">FEAT_MPAMv0p1</xref> or <xref linkend="#FEAT_MPAMv1p0">FEAT_MPAMv1p0</xref> is implemented, then the following statements apply:</para>

      </configuration_text>
      <configuration_text>
        <list type="unordered">
<listitem><content>
<para>The MPAMCFG_MBW_PBM&lt;n&gt;_s registers control the bandwidth portion bitmap for the Secure PARTID selected by the Secure instance of <register_link state="ext" id="ext-mpamcfg_part_sel.xml">MPAMCFG_PART_SEL</register_link>.</para>
</content>
</listitem><listitem><content>
<para>The MPAMCFG_MBW_PBM&lt;n&gt;_ns registers control the bandwidth portion bitmap for the Non-secure PARTID selected by the Non-secure instance of <register_link state="ext" id="ext-mpamcfg_part_sel.xml">MPAMCFG_PART_SEL</register_link>.</para>
</content>
</listitem><listitem><content>
<para>If <xref linkend="#FEAT_RME">FEAT_RME</xref> is implemented, then the following statements also apply:</para>
<list type="unordered">
<listitem><content>
<para>The MPAMCFG_MBW_PBM&lt;n&gt;_rt registers control the bandwidth portion bitmap for the Root PARTID selected by the Root instance of <register_link state="ext" id="ext-mpamcfg_part_sel.xml">MPAMCFG_PART_SEL</register_link>.</para>
</content>
</listitem><listitem><content>
<para>The MPAMCFG_MBW_PBM&lt;n&gt;_rl registers control the bandwidth portion bitmap for the Realm PARTID selected by the Realm instance of <register_link state="ext" id="ext-mpamcfg_part_sel.xml">MPAMCFG_PART_SEL</register_link>.</para>
</content>
</listitem></list>
</content>
</listitem></list>

      </configuration_text>
      <configuration_text>
        <para>The power and reset domain of each MSC component is specific to that component.</para>
      </configuration_text>

      </reg_configuration>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>MPAMCFG_MBW_PBM&lt;n&gt; is a 32-bit register.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="32">
  <text_before_fields/>
  <field id="fieldset_0-31_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>P&lt;x&gt;</field_name>
    <field_msb>31</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>31:0</rel_range>
    <field_description order="before">
      <para>Portion allocation control bit. Each bandwidth portion allocation control bit MPAMCFG_MBW_PBM&lt;n&gt;.P&lt;x&gt; grants permission to the PARTID selected by <register_link state="ext" id="ext-mpamcfg_part_sel.xml">MPAMCFG_PART_SEL</register_link> to allocate bandwidth within bandwidth portion &lt;32*n&gt; + &lt;x&gt;.</para>
    </field_description>
    <field_description order="after">
      <para>The number of bits in the bandwidth portion partitioning bit map of this component is given in <register_link state="ext" id="ext-mpamf_mbw_idr.xml">MPAMF_MBW_IDR</register_link>.BWPBM_WD. BWPBM_WD contains a value from 1 to 2<sup>12</sup>, inclusive. Values of <register_link state="ext" id="ext-mpamf_mbw_idr.xml">MPAMF_MBW_IDR</register_link>.BWPBM_WD greater than 32 require a group of 32-bit registers to access the bandwidth portion bitmap, up to 128 32-bit registers.</para>
    </field_description>
    <field_array_indexes index_variable="x" element_size="1" range_specifier="x">
      <field_array_index>
        <field_array_start>31</field_array_start>
        <field_array_end>0</field_array_end>
      </field_array_index>
    </field_array_indexes>
    <field_values impdef="False">
      <field_value_instance>
        <field_value>0b0</field_value>
        <field_value_description>
          <para>The PARTID is not permitted to allocate into bandwidth portion &lt;32*n&gt; + &lt;x&gt;.</para>
        </field_value_description>
      </field_value_instance>
      <field_value_instance>
        <field_value>0b1</field_value>
        <field_value_description>
          <para>The PARTID is permitted to allocate within bandwidth portion &lt;32*n&gt; + &lt;x&gt;.</para>
        </field_value_description>
      </field_value_instance>
    </field_values>
    <field_access>
      <field_access_state>
        <field_access_level>When (n * 32) + x &gt; UInt(MPAMF_MBW_IDR().BWPBM_WD)</field_access_level>
        <field_access_type>
          <arm-defined-word>RES0</arm-defined-word>
        </field_access_type>
      </field_access_state>
    </field_access>
  </field>
  <text_after_fields/>
</fields>




<reg_fieldset length="32">
  <fieldat id="fieldset_0-31_0" label="P31" msb="31" lsb="31"/>
  <fieldat id="fieldset_0-31_0" label="P30" msb="30" lsb="30"/>
  <fieldat id="fieldset_0-31_0" label="P29" msb="29" lsb="29"/>
  <fieldat id="fieldset_0-31_0" label="P28" msb="28" lsb="28"/>
  <fieldat id="fieldset_0-31_0" label="P27" msb="27" lsb="27"/>
  <fieldat id="fieldset_0-31_0" label="P26" msb="26" lsb="26"/>
  <fieldat id="fieldset_0-31_0" label="P25" msb="25" lsb="25"/>
  <fieldat id="fieldset_0-31_0" label="P24" msb="24" lsb="24"/>
  <fieldat id="fieldset_0-31_0" label="P23" msb="23" lsb="23"/>
  <fieldat id="fieldset_0-31_0" label="P22" msb="22" lsb="22"/>
  <fieldat id="fieldset_0-31_0" label="P21" msb="21" lsb="21"/>
  <fieldat id="fieldset_0-31_0" label="P20" msb="20" lsb="20"/>
  <fieldat id="fieldset_0-31_0" label="P19" msb="19" lsb="19"/>
  <fieldat id="fieldset_0-31_0" label="P18" msb="18" lsb="18"/>
  <fieldat id="fieldset_0-31_0" label="P17" msb="17" lsb="17"/>
  <fieldat id="fieldset_0-31_0" label="P16" msb="16" lsb="16"/>
  <fieldat id="fieldset_0-31_0" label="P15" msb="15" lsb="15"/>
  <fieldat id="fieldset_0-31_0" label="P14" msb="14" lsb="14"/>
  <fieldat id="fieldset_0-31_0" label="P13" msb="13" lsb="13"/>
  <fieldat id="fieldset_0-31_0" label="P12" msb="12" lsb="12"/>
  <fieldat id="fieldset_0-31_0" label="P11" msb="11" lsb="11"/>
  <fieldat id="fieldset_0-31_0" label="P10" msb="10" lsb="10"/>
  <fieldat id="fieldset_0-31_0" label="P9" msb="9" lsb="9"/>
  <fieldat id="fieldset_0-31_0" label="P8" msb="8" lsb="8"/>
  <fieldat id="fieldset_0-31_0" label="P7" msb="7" lsb="7"/>
  <fieldat id="fieldset_0-31_0" label="P6" msb="6" lsb="6"/>
  <fieldat id="fieldset_0-31_0" label="P5" msb="5" lsb="5"/>
  <fieldat id="fieldset_0-31_0" label="P4" msb="4" lsb="4"/>
  <fieldat id="fieldset_0-31_0" label="P3" msb="3" lsb="3"/>
  <fieldat id="fieldset_0-31_0" label="P2" msb="2" lsb="2"/>
  <fieldat id="fieldset_0-31_0" label="P1" msb="1" lsb="1"/>
  <fieldat id="fieldset_0-31_0" label="P0" msb="0" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>
        <reg_variables>
              <reg_variable variable="n" max="127"/>
        </reg_variables>

      <access_mechanisms>
          


  
    
      <access_permission_text>
        <para>If both <xref linkend="#FEAT_MPAM">FEAT_MPAM</xref> and <xref linkend="#FEAT_RME">FEAT_RME</xref> are implemented, the following statements apply:</para>

      </access_permission_text>
      <access_permission_text>
        <list type="unordered">
<listitem><content>
<para>In a system that supports Secure, Non-secure, Root, and Realm memory maps, there must be MPAM feature pages in all four address maps:</para>
</content>
</listitem><listitem><content>
<para>MPAMCFG_MBW_PBM&lt;n&gt;_s must only be accessible from the Secure MPAM feature page.</para>
</content>
</listitem><listitem><content>
<para>MPAMCFG_MBW_PBM&lt;n&gt;_ns must only be accessible from the Non-secure MPAM feature page.</para>
</content>
</listitem><listitem><content>
<para>MPAMCFG_MBW_PBM&lt;n&gt;_rt must only be accessible from the Root MPAM feature page.</para>
</content>
</listitem><listitem><content>
<para>MPAMCFG_MBW_PBM&lt;n&gt;_rl must only be accessible from the Realm MPAM feature page.</para>
</content>
</listitem><listitem><content>
<para>MPAMCFG_MBW_PBM&lt;n&gt;_s, MPAMCFG_MBW_PBM&lt;n&gt;_ns, MPAMCFG_MBW_PBM&lt;n&gt;_rt, and MPAMCFG_MBW_PBM&lt;n&gt;_rl must be separate registers:</para>
</content>
</listitem><listitem><content>
<para>The Secure instance (MPAMCFG_MBW_PBM&lt;n&gt;_s) accesses the memory bandwidth portion bitmap used for Secure PARTIDs.</para>
</content>
</listitem><listitem><content>
<para>The Non-secure instance (MPAMCFG_MBW_PBM&lt;n&gt;_ns) accesses the memory bandwidth portion bitmap used for Non-secure PARTIDs.</para>
</content>
</listitem><listitem><content>
<para>The Root instance (MPAMCFG_MBW_PBM&lt;n&gt;_rt) accesses the memory bandwidth portion bitmap used for Root PARTIDs.</para>
</content>
</listitem><listitem><content>
<para>The Realm instance (MPAMCFG_MBW_PBM&lt;n&gt;_rl) accesses the memory bandwidth portion bitmap used for Realm PARTIDs.</para>
</content>
</listitem></list>

      </access_permission_text>
      <access_permission_text>
        <para>When RIS is implemented, loads and stores to MPAMCFG_MBW_PBM&lt;n&gt; access the memory bandwidth portion bitmap configuration settings for the bandwidth resource instance selected by <register_link state="ext" id="ext-mpamcfg_part_sel.xml">MPAMCFG_PART_SEL</register_link>.RIS and the PARTID selected by <register_link state="ext" id="ext-mpamcfg_part_sel.xml">MPAMCFG_PART_SEL</register_link>.PARTID_SEL.</para>

      </access_permission_text>
      <access_permission_text>
        <para>When RIS is not implemented, loads and stores to MPAMCFG_MBW_PBM&lt;n&gt; access the memory bandwidth portion bitmap configuration settings for the PARTID selected by <register_link state="ext" id="ext-mpamcfg_part_sel.xml">MPAMCFG_PART_SEL</register_link>.PARTID_SEL.</para>

      </access_permission_text>
      <access_permission_text>
        <para>When PARTID narrowing is implemented, loads and stores to MPAMCFG_MBW_PBM&lt;n&gt; access the memory bandwidth portion bitmap configuration settings for the internal PARTID selected by <register_link state="ext" id="ext-mpamcfg_part_sel.xml">MPAMCFG_PART_SEL</register_link>.PARTID_SEL, and <register_link state="ext" id="ext-mpamcfg_part_sel.xml">MPAMCFG_PART_SEL</register_link>.INTERNAL must be 1.</para>

      </access_permission_text>
      <access_permission_text>
        <para>When PARTID narrowing is not implemented, loads and stores to MPAMCFG_MBW_PBM&lt;n&gt; access the memory bandwidth portion bitmap configuration settings for the request PARTID selected by <register_link state="ext" id="ext-mpamcfg_part_sel.xml">MPAMCFG_PART_SEL</register_link>.PARTID_SEL, and <register_link state="ext" id="ext-mpamcfg_part_sel.xml">MPAMCFG_PART_SEL</register_link>.INTERNAL must be 0.</para>
      </access_permission_text>





    
    
    
    

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>