MPAMF_CCAP_IDR MPAM Features Cache Capacity Partitioning ID register The power domain of MPAMF_CCAP_IDR is IMPLEMENTATION DEFINED when (FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p0 is implemented) and MPAMF_IDR.HAS_CCAP_PART == '1' MPAM MPAMF_BASE_s 0x0038 MPAMF_CCAP_IDR_s When FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented RO MPAM MPAMF_BASE_ns 0x0038 MPAMF_CCAP_IDR_ns When FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented RO MPAM MPAMF_BASE_rt 0x0038 MPAMF_CCAP_IDR_rt When FEAT_RME is implemented and (FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented) RO MPAM MPAMF_BASE_rl 0x0038 MPAMF_CCAP_IDR_rl When FEAT_RME is implemented and (FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented) RO Indicates the number of fractional bits in MPAMCFG_CMAX.CMAX. MPAM If MPAMF_IDR.HAS_RIS is 1, some fields in this register give information for the resource instance currently selected by MPAMCFG_PART_SEL.RIS. The description of every field affected by MPAMCFG_PART_SEL.RIS has information within the field description. If FEAT_MPAMv1p0 or FEAT_MPAMv0p1 is implemented, then the following statements apply: MPAMF_CCAP_IDR_s indicates the number of fractional bits in the Secure instance of MPAMCFG_CMAX. MPAMF_CCAP_IDR_ns indicates the number of fractional bits in the Non-secure instance of MPAMCFG_CMAX. If FEAT_RME is implemented, the following statements also apply: MPAMF_CCAP_IDR_rt indicates the number of fractional bits in the Root cache capacity control settings register field, MPAMCFG_CMAX.CMAX. MPAMF_CCAP_IDR_rl indicates the number of fractional bits in the Realm cache capacity control settings register field, MPAMCFG_CMAX.CMAX. The power and reset domain of each MSC component is specific to that component. MPAMF_CCAP_IDR is a 32-bit register. HAS_CMAX_SOFTLIM 31 31 0 Has soft limiting selection field in MPAMCFG_CMAX. If RIS is implemented, this field indicates selectable limiting for the cache maximum capacity control for the resource instance selected by MPAMCFG_PART_SEL.RIS. 0b0 If MPAMCFG_CMAX is implemented, it has no SOFTLIM field and the maximum capacity is controlled with a hard limit. 0b1 If MPAMCFG_CMAX is implemented, that register has a SOFTLIMIT field to select between hard or soft limiting to the CMAX parameter. RO When FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p1 is implemented 31 31 31 Reserved, RES0. Otherwise NO_CMAX 30 30 0 Does not have CMAX partitioning. If RIS is implemented, this field indicates the absence of a cache maximum capacity partitioning control for the resource instance selected by MPAMCFG_PART_SEL.RIS. 0b0 MPAMCFG_CMAX is implemented. 0b1 MPAMCFG_CMAX is not implemented. RO When FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p1 is implemented 30 30 30 Reserved, RES0. Otherwise HAS_CMIN 29 29 0 Has cache minimum capacity partitioning. If RIS is implemented, this field indicates the presence of a cache minimum capacity partitioning control for the resource instance selected by MPAMCFG_PART_SEL.RIS. 0b0 MPAMCFG_CMIN is not implemented. 0b1 MPAMCFG_CMIN is implemented. RO When FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p1 is implemented 29 29 29 Reserved, RES0. Otherwise HAS_CASSOC 28 28 0 Has cache maximum associativity partitioning. If RIS is implemented, this field indicates the presence of a cache maximum associativity partitioning control for the resource instance selected by MPAMCFG_PART_SEL.RIS. 0b0 MPAMCFG_CASSOC is not implemented. 0b1 MPAMCFG_CASSOC is implemented. RO When FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p1 is implemented 28 28 28 Reserved, RES0. Otherwise 27 13 27:13 Reserved, RES0. CASSOC_WD 12 8 4:0 Number of fractional bits implemented in the cache associativity partitioning control, MPAMCFG_CASSOC.CASSOC, of this MSC. See MPAMCFG_CASSOC. If RIS is implemented, this field indicates the number of fractional bits in the cache capacity partitioning control for the resource instance selected by MPAMCFG_PART_SEL.RIS. This field has an IMPLEMENTATION DEFINED value. RO When FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p1 is implemented 12 8 12:8 Reserved, RES0. Otherwise 7 6 7:6 Reserved, RES0. CMAX_WD 5 0 5:0 Number of fractional bits implemented in the cache capacity partitioning control, MPAMCFG_CMAX.CMAX, of this device. See MPAMCFG_CMAX. This field must contain a value from 1 to 16, inclusive. If RIS is implemented, this field indicates the number of fractional bits in the cache capacity partitioning control for the resource instance selected by MPAMCFG_PART_SEL.RIS. This field has an IMPLEMENTATION DEFINED value. RO If both FEAT_MPAM and FEAT_RME are implemented, the following statements apply: In a system that supports Secure, Non-secure, Root, and Realm memory maps, there must be MPAM feature pages in all four address maps. MPAMF_CCAP_IDR must be readable from the Non-secure, Secure, Root, and Realm MPAM feature pages. MPAMF_CCAP_IDR is permitted to have the same contents when read from the Secure, Non-secure, Root, and Realm MPAM feature pages unless the register contents are different for the different versions: MPAMF_CCAP_IDR_s is permitted to have either the same or different contents to MPAMF_CCAP_IDR_ns, MPAMF_CCAP_IDR_rt, or MPAMF_CCAP_IDR_rl. MPAMF_CCAP_IDR_ns is permitted to have either the same or different contents to MPAMF_CCAP_IDR_rt or MPAMF_CCAP_IDR_rl. MPAMF_CCAP_IDR_rt is permitted to have either the same or different contents to MPAMF_CCAP_IDR_rl. There must be separate registers in the Secure (MPAMF_CCAP_IDR_s), Non-secure (MPAMF_CCAP_IDR_ns), Root (MPAMF_CCAP_IDR_rt), and Realm (MPAMF_CCAP_IDR_rl) MPAM feature pages. If any one of these features is implemented: FEAT_MPAMv0p1 FEAT_MPAMv1p1 then, the following statements apply: When MPAMF_IDR.HAS_RIS is 1, MPAMF_CCAP_IDR shows the configuration of cache capacity partitioning for the cache resource instance selected by MPAMCFG_PART_SEL.RIS. Fields that mention RIS in their field descriptions have values that track the implemented properties of the resource instance. Fields that do not mention RIS are constant across all resource instances. 2026-03-26 20:27:25 2026-03_rel