MPAMF_CSAMON_IDR MPAM Features Cache Storage Allocation Monitoring ID register The power domain of MPAMF_CSAMON_IDR is IMPLEMENTATION DEFINED when FEAT_MPAM_MSC_MSMON is implemented and FEAT_MPAM_CSA is implemented MPAM MPAMF_BASE_s 0x0098 MPAMF_CSAMON_IDR_s When FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented RO MPAM MPAMF_BASE_ns 0x0098 MPAMF_CSAMON_IDR_ns When FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented RO MPAM MPAMF_BASE_rt 0x0098 MPAMF_CSAMON_IDR_rt When FEAT_RME is implemented and (FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented) RO MPAM MPAMF_BASE_rl 0x0098 MPAMF_CSAMON_IDR_rl When FEAT_RME is implemented and (FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented) RO Indicates the number of cache storage allocation monitor instances and other properties of the CSA monitoring. Identification Registers If MPAMF_IDR.HAS_RIS is 1, fields that mention RIS must reflect the properties of the resource instance currently selected by MPAMCFG_PART_SEL.RIS. Fields that do not mention RIS are constant across all resource instances. If FEAT_MPAMv0p1 or FEAT_MPAMv1p0 is implemented, the register is banked and the following statements apply: MPAMF_CSAMON_IDR_s indicates the number and properties of Secure cache storage allocation monitoring. MPAMF_CSAMON_IDR_ns indicates the number and properties of Non-secure cache storage allocation monitoring. If FEAT_RME is implemented the following statements also apply: MPAMF_CSAMON_IDR_rt indicates the number and properties of Root cache storage allocation monitoring. MPAMF_CSAMON_IDR_rl indicates the number and properties of Realm cache storage allocation monitoring. The power and reset domain of each MSC component is specific to that component. MPAMF_CSAMON_IDR is a 32-bit register. When FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented HAS_CAPTURE 31 31 31 The implementation supports copying an MSMON_CSA to the corresponding MSMON_CSA_CAPTURE on a capture event. If MPAMF_IDR.HAS_RIS is 1, this field reports that CSA monitor capture is implemented for the resource instance selected by MPAMCFG_PART_SEL.RIS. If MPAMF_CSAMON_IDR.HAS_LONG is 1, this field also reports that MSMON_CSA_L_CAPTURE is implemented. 0b0 MSMON_CSA_CAPTURE is not implemented and there is no support for capture events in the CSA monitor. 0b1 The MSMON_CSA_CAPTURE register is implemented and the CSA monitor supports the capture event behavior. RO HAS_LONG 30 30 0 Reports whether MSMON_CSA_L is implemented. If MPAMF_IDR.HAS_RIS is 1, this field reports that the long CSA monitor is implemented for the resource instance selected by MPAMCFG_PART_SEL.RIS. If MPAMF_CSAMON_IDR.HAS_CAPTURE is 1, this field also reports that MSMON_CSA_L_CAPTURE is implemented. 0b0 MSMON_CSA_L is not implemented. If MPAMF_CSAMON_IDR.HAS_CAPTURE is 1, MSMON_CSA_L_CAPTURE is also not implemented. 0b1 MSMON_CSA_L is implemented. If MPAMF_CSAMON_IDR.HAS_CAPTURE is 1, MSMON_CSA_L_CAPTURE is also implemented. RO When FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p1 is implemented 30 30 30 Reserved, RES0. Otherwise LWD 29 29 0 Long register VALUE width. If MPAMF_IDR.HAS_RIS is 1, this field reports the length of the MSMON_CSA_L.VALUE field implemented for the resource instance selected by MPAMCFG_PART_SEL.RIS. 0b0 MSMON_CSA_L has 44-bit VALUE field in bits [43:0]. Bits [62:44] are RES0. If MPAMF_CSAMON_IDR.HAS_CAPTURE is 1, MSMON_CSA_L_CAPTURE also has 44-bit VALUE field in bits [43:0]. 0b1 MSMON_CSA_L has 63-bit VALUE field in bits [62:0]. If MPAMF_CSAMON_IDR.HAS_CAPTURE is 1, MSMON_CSA_L_CAPTURE also has 63-bit VALUE field in bits [62:0]. RO When (FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p1 is implemented) and MPAMF_CSAMON_IDR.HAS_LONG == '1' 29 29 29 Reserved, RES0. Otherwise 28 28 28 Reserved, RES0. HAS_OFLOW_LNKG 27 27 0 Supports MSMON_CFG_CSA_CTL.OFLOW_LNKG field to control how overflow on an instance affects other monitor instances in this MSC. If MPAMF_IDR.HAS_RIS is 1, this field reports that MSMON_CFG_CSA_CTL.OFLOW_LNKG is implemented for the resource instance selected by MPAMCFG_PART_SEL.RIS. 0b0 Does not support CSA overflow linkage. 0b1 Supports CSA overflow linkage and the MSMON_CFG_CSA_CTL.OFLOW_LNKG field. RO When FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p1 is implemented 27 27 27 Reserved, RES0. Otherwise HAS_OFSR 26 26 0 The CSA monitor overflow status bitmap register, MSMON_CSA_OFSR, is implemented. If MPAMF_IDR.HAS_RIS is 1, this field reports that the CSA monitor overflow status bitmap register is implemented for the resource instance selected by MPAMCFG_PART_SEL.RIS. 0b0 MSMON_CSA_OFSR register is not implemented. 0b1 MSMON_CSA_OFSR register is implemented. RO When FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p1 is implemented 26 26 26 Reserved, RES0. Otherwise HAS_CEVNT_OFLW 25 25 0 Supports MSMON_CFG_CSA_CTL.CEVNT_OFLW field which can enable the CSA monitor instance to perform overflow behaviors on a capture event. If MPAMF_IDR.HAS_RIS is 1, this field reports that MSMON_CFG_CSA_CTL.CEVNT_OFLW is implemented for the resource instance selected by MPAMCFG_PART_SEL.RIS. 0b0 Does not support MSMON_CFG_CSA_CTL.CEVNT_OFLW. 0b1 Supports MSMON_CFG_CSA_CTL.CEVNT_OFLW. RO When FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p1 is implemented 25 25 25 Reserved, RES0. Otherwise HAS_OFLOW_CAPT 24 24 0 Supports MSMON_CFG_CSA_CTL.OFLOW_CAPT field which can enable the CSA monitor instance to capture the monitor on an overflow. If MPAMF_IDR.HAS_RIS is 1, this field reports that MSMON_CFG_CSA_CTL.OFLOW_CAPT is implemented for the resource instance selected by MPAMCFG_PART_SEL.RIS. 0b0 Does not support MSMON_CFG_CSA_CTL.OFLOW_CAPT. 0b1 Supports MSMON_CFG_CSA_CTL.OFLOW_CAPT. RO When FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p1 is implemented 24 24 24 Reserved, RES0. Otherwise NO_MATCH_PARTID 23 23 23 Indicates support for using PARTID identifiers for monitoring. 0b0 Supports cache storage allocation monitoring based on PARTID. 0b1 Does not support cache storage allocation monitoring based on PARTID. RO NO_MATCH_PMG 22 22 22 Indicates support for using PMG identifiers for monitoring. 0b0 Supports cache storage allocation monitoring based on PMG. 0b1 Does not support cache storage allocation monitoring based on PMG. RO 21 21 21 Reserved, RES0. SCALE 20 16 20:16 Scaling of MSMON_CSA.VALUE in bits. If scaling is enabled by MSMON_CFG_CSA_CTL.SCLEN, the byte count in the VALUE field has been shifted by SCALE bits to the right. If MPAMF_IDR.HAS_RIS is 1, this field reports the scale value for MSMON_CSA.VALUE field for the resource instance selected by MPAMCFG_PART_SEL.RIS. This field has an IMPLEMENTATION DEFINED value. RO NUM_MON 15 0 15:0 The number of cache storage allocation monitor instances implemented. The largest MSMON_CFG_MON_SEL.MON_SEL value is NUM_MON minus 1. If MPAMF_IDR.HAS_RIS is 1, this field reports the number of CSA monitor instances implemented for the resource instance selected by MPAMCFG_PART_SEL.RIS. This field has an IMPLEMENTATION DEFINED value. RO When FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented This register is within the MPAM feature page memory frames. If FEAT_MPAM is implemented, the following statements apply: In a system that supports Secure and Non-secure memory maps, there must be both Secure and Non-secure MPAM feature pages. MPAMF_CSAMON_IDR must be readable from the Non-secure and Secure MPAM feature pages. MPAMF_CSAMON_IDR is permitted to have the same contents when read from the Secure or Non-secure MPAM feature pages unless the register contents are different for the different versions, when MPAMF_CSAMON_IDR_s is permitted to have either the same or different contents to MPAMF_CSAMON_IDR_ns. There must be separate registers in the Secure (MPAMF_CSAMON_IDR_s) and Non-secure (MPAMF_CSAMON_IDR_ns) MPAM feature pages. If both FEAT_MPAM and FEAT_RME are implemented, the following statements apply: In a system that supports Secure, Non-secure, Root, and Realm memory maps, there must be MPAM feature pages in all four address maps. MPAMF_CSAMON_IDR must be readable from the Non-secure, Secure, Root, and Realm MPAM feature pages. MPAMF_CSAMON_IDR is permitted to have the same contents when read from the Secure, Non-secure, Root, and Realm MPAM feature pages unless the register contents are different for the different versions: MPAMF_CSAMON_IDR_s is permitted to have either the same or different contents to MPAMF_CSAMON_IDR_ns, MPAMF_CSAMON_IDR_rt, or MPAMF_CSAMON_IDR_rl. MPAMF_CSAMON_IDR_ns is permitted to have either the same or different contents to MPAMF_CSAMON_IDR_rt or MPAMF_CSAMON_IDR_rl. MPAMF_CSAMON_IDR_rt is permitted to have either the same or different contents to MPAMF_CSAMON_IDR_rl. There must be separate registers in the Secure (MPAMF_CSAMON_IDR_s), Non-secure (MPAMF_CSAMON_IDR_ns), Root (MPAMF_CSAMON_IDR_rt), and Realm (MPAMF_CSAMON_IDR_rl) MPAM feature pages. If any one of these features is implemented: FEAT_MPAMv0p1 FEAT_MPAMv1p1 then, the following statements apply: When MPAMF_IDR.HAS_RIS is 1, MPAMF_CSAMON_IDR shows the configuration of cache storage allocation monitoring for the cache resource instance selected by MPAMCFG_PART_SEL.RIS. Fields that mention RIS in their field descriptions have values that track the implemented properties of the resource instance. Fields that do not mention RIS are constant across all resource instances. Access to MPAMF_CSAMON_IDR is not affected by MSMON_CFG_MON_SEL.RIS. 2026-03-26 20:27:25 2026-03_rel