MPAMF_ESR MPAM Error Status Register The power domain of MPAMF_ESR is IMPLEMENTATION DEFINED when FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p0 is implemented MPAM MPAMF_BASE_s 0x00F8 MPAMF_ESR_s When FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented RW MPAM MPAMF_BASE_ns 0x00F8 MPAMF_ESR_ns When FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented RW MPAM MPAMF_BASE_rt 0x00F8 MPAMF_ESR_rt When FEAT_RME is implemented and (FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented) RW MPAM MPAMF_BASE_rl 0x00F8 MPAMF_ESR_rl When FEAT_RME is implemented and (FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented) RW Indicates MPAM error status for this MSC. Software should write this register after reading the status of an error to reset ERRCODE to 0x0000 and OVRWR to 0 so that future errors are not reported with OVRWR set. MPAM If an MSC cannot encounter any of the error conditions listed in MPAM MSC Errors of Arm® Memory System Resource Partitioning and Monitoring (MPAM) System Component Specification (ARM IHI 0099), both the MPAMF_ESR and MPAMF_ECR must be RAZ/WI. If FEAT_MPAMv1p0 or FEAT_MPAMv0p1 is implemented, then the following statements apply: MPAMF_ESR_s reports Secure MPAM errors. MPAMF_ESR_ns reports Non-secure MPAM errors. If FEAT_RME is implemented, then the following statements also apply: MPAMF_ESR_rt reports Root MPAM errors. MPAMF_ESR_rl reports Realm MPAM errors. The power and reset domain of each MSC component is specific to that component. MPAMF_ESR is a: 64-bit register when (FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p1 is implemented) and MPAMF_IDR.HAS_EXTD_ESR == '1' 32-bit register otherwise When (FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p1 is implemented) and MPAMF_IDR.HAS_EXTD_ESR == '1' 63 36 63:36 Reserved, RES0. RIS 35 32 3:0 Resource Instance Selector. Where applicable to the ERRCODE, captures the RIS value for the error. When MPAMF_IDR.HAS_RIS == '1' 35 32 35:32 Reserved, RES0. Otherwise OVRWR 31 31 31 Overwritten. If 0 and ERRCODE == 0b0000, no errors have occurred. If 0 and ERRCODE is nonzero, a single error has occurred and is recorded in this register. If 1 and ERRCODE is nonzero, multiple errors have occurred and this register records the most recent error. The state where this bit is 1 and ERRCODE is zero must not be produced by hardware and is only reached when software writes this combination into this register. 30 28 30:28 Reserved, RES0. ERRCODE 27 24 27:24 Error code. 0b0000 No error. 0b0001 PARTID_SEL_Range. 0b0010 Req_PARTID_Range. 0b0011 MSMONCFG_ID_RANGE. 0b0100 Req_PMG_Range. 0b0101 Monitor_Range. 0b0110 intPARTID_Range. 0b0111 Unexpected_INTERNAL. 0b1000 Undefined_RIS_PART_SEL. 0b1001 RIS_No_Control. 0b1010 Undefined_RIS_MON_SEL. 0b1011 RIS_No_Monitor. 0b1100 Reserved. 0b1101 Reserved. 0b1110 Reserved. 0b1111 Reserved. PMG 23 16 23:16 Program monitoring group. Set to the PMG on an error that captures PMG. Otherwise, set to 0x00 on an error that does not capture PMG. PARTID_MON 15 0 15:0 PARTID or monitor. Set to the PARTID on an error that captures PARTID. Set to the monitor index on an error that captures MON. On an error that captures neither PARTID nor MON, this field is set to 0. OVRWR 31 31 31 Overwritten. If 0 and ERRCODE == 0b0000, no errors have occurred. If 0 and ERRCODE is nonzero, a single error has occurred and is recorded in this register. If 1 and ERRCODE is nonzero, multiple errors have occurred and this register records the most recent error. The state where this bit is 1 and ERRCODE is 0 must not be produced by hardware and is only reached when software writes this combination into this register. 30 28 30:28 Reserved, RES0. ERRCODE 27 24 27:24 Error code. 0b0000 No error. 0b0001 PARTID_SEL_Range. 0b0010 Req_PARTID_Range. 0b0011 MSMONCFG_ID_RANGE. 0b0100 Req_PMG_Range. 0b0101 Monitor_Range. 0b0110 intPARTID_Range. 0b0111 Unexpected_INTERNAL. 0b1000 Reserved. 0b1001 Reserved. 0b1010 Reserved. 0b1011 Reserved. 0b1100 Reserved. 0b1101 Reserved. 0b1110 Reserved. 0b1111 Reserved. PMG 23 16 23:16 Program monitoring group. Set to the PMG on an error that captures PMG. Otherwise, set to 0x00 on an error that does not capture PMG. PARTID_MON 15 0 15:0 PARTID or monitor. Set to the PARTID on an error that captures PARTID. Set to the monitor index on an error that captures MON. On an error that captures neither PARTID nor MON, this field is set to 0x0000. When (FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p1 is implemented) and MPAMF_IDR.HAS_EXTD_ESR == '1' If both FEAT_MPAM and FEAT_RME are implemented, the following statements apply: In a system that supports Secure, Non-secure, Root, and Realm memory maps, there must be MPAM feature pages in all four address maps: MPAMF_ESR_s must only be accessible from the Secure MPAM feature page. MPAMF_ESR_ns must only be accessible from the Non-secure MPAM feature page. MPAMF_ESR_rt must only be accessible from the Root MPAM feature page. MPAMF_ESR_rl must only be accessible from the Realm MPAM feature page. MPAMF_ESR_s, MPAMF_ESR_ns, MPAMF_ESR_rt, and MPAMF_ESR_rl must be separate registers: The Secure instance (MPAMF_ESR_s) accesses the error status used for Secure PARTIDs. The Non-secure instance (MPAMF_ESR_ns) accesses the error status used for Non-secure PARTIDs. The Root instance (MPAMF_ESR_rt) accesses the error status used for Root PARTIDs. The Realm instance (MPAMF_ESR_rl) accesses the error status used for Realm PARTIDs. 2026-03-26 20:27:25 2026-03_rel