MPAMF_IDR MPAM Features Identification Register The power domain of MPAMF_IDR is IMPLEMENTATION DEFINED when FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p0 is implemented MPAM MPAMF_BASE_s 0x0000 MPAMF_IDR_s When FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented RO MPAM MPAMF_BASE_ns 0x0000 MPAMF_IDR_ns When FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented RO MPAM MPAMF_BASE_rt 0x0000 MPAMF_IDR_rt When FEAT_RME is implemented and (FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented) RO MPAM MPAMF_BASE_rl 0x0000 MPAMF_IDR_rl When FEAT_RME is implemented and (FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented) RO Indicates which memory partitioning and monitoring features are present on this MSC. Identification Registers If FEAT_MPAMv1p0 or FEAT_MPAMv0p1 is implemented, the following statements apply: MPAMF_IDR_s indicates the MPAM features accessed from the Secure MPAM feature page. MPAMF_IDR_ns indicates the MPAM features accessed from the Non-secure MPAM feature page. If both FEAT_MPAMv1p0 or FEAT_MPAMv0p1 is implemented and FEAT_RME are implemented, the following statements apply: MPAMF_IDR_rt indicates the MPAM features accessed from the Root MPAM feature page. MPAMF_IDR_rl indicates the MPAM features accessed from the Realm MPAM feature page. If any one of these features is implemented: FEAT_MPAMv0p1 FEAT_MPAMv1p1 then, the following statements apply: When MPAMF_IDR.HAS_RIS is 1, some fields in this register give information for the resource instance selected by MPAMCFG_PART_SEL.RIS. The description of every field that is affected by MPAMCFG_PART_SEL.RIS has that information within the field description. The power and reset domain of each MSC component is specific to that component. MPAMF_IDR is a: 64-bit register when FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p1 is implemented 32-bit register otherwise When FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p1 is implemented 63 60 63:60 Reserved, RES0. RIS_MAX 59 56 3:0 Maximum RIS value supported in MPAMCFG_PART_SEL. Must be 0b0000 if MPAMF_IDR.HAS_RIS == 0. This field has an IMPLEMENTATION DEFINED value. RO When MPAMF_IDR.EXT == '1' and MPAMF_IDR.HAS_RIS == '1' 59 56 59:56 Reserved, RES0. Otherwise 55 47 55:47 Reserved, RES0. HAS_DEFAULT_PARTID 46 46 0 Indicates support in an MSC for a default resource control configuration. FEAT_MPAM_MSC_DCTRL implements the functionality identified by the value 1. 0b0 The default resource control configuration is supported. 0b1 The default resource control configuration is not supported. RO When MPAMF_IDR.EXT == '1' 46 46 46 Reserved, RES0. Otherwise HAS_OUT_TL 45 45 0 Has egress translation. Indicates that this MSC supports egress MPAM information bundle manipulation. 0b0 MPAM information bundle manipulation for egress translation is not supported. 0b1 MPAM information bundle manipulation for egress translation is supported. RO When MPAMF_IDR.EXT == '1' 45 45 45 Reserved, RES0. Otherwise HAS_IN_TL 44 44 0 Has ingress translation. Indicates that this MSC supports ingress MPAM information bundle manipulation. 0b0 MPAM information bundle manipulation for ingress translation is not supported. 0b1 MPAM information bundle manipulation for ingress translation is supported. RO When MPAMF_IDR.EXT == '1' 44 44 44 Reserved, RES0. Otherwise HAS_NFU 43 43 0 Has No Future Use field in MPAMCFG_DIS. Indicates that MPAMCFG_DIS.NFU is implemented. If MPAMF_IDR.HAS_ENDIS is 0, this field must also be 0. This field must be the same in each instance of this register and for any value in MPAMCFG_PART_SEL.RIS. 0b0 MPAMCFG_DIS.NFU is not implemented. A PARTID disabled through access to MPAMCFG_DIS must preserve the control settings of the disabled PARTID. 0b1 Implements MPAMCFG_DIS.NFU. A PARTID disabled with NFU as 1 may have its control settings forgotten. RO When MPAMF_IDR.EXT == '1' 43 43 43 Reserved, RES0. Otherwise HAS_ENDIS 42 42 0 Has PARTID enable and disable. Indicates that this MSC supports PARTID disable and enable via MPAMCFG_DIS, MPAMCFG_EN and MPAMCFG_EN_FLAGS registers. All three registers must be implemented when this field is 1, MPAMCFG_EN, MPAMCFG_DIS, and MPAMCFG_EN_FLAGS. This field must be the same in each instance of this register and for any value in MPAMCFG_PART_SEL.RIS. 0b0 Does not support PARTID enable and disable functionality, and MPAMCFG_EN, MPAMCFG_DIS and MPAMCFG_EN_FLAGS registers are not implemented. 0b1 Supports PARTID enable and disable through the MPAMCFG_EN, MPAMCFG_DIS and MPAMCFG_EN_FLAGS registers. RO When MPAMF_IDR.EXT == '1' 42 42 42 Reserved, RES0. Otherwise SP4 41 41 0 Indicates whether this MSC supports 4 PARTID spaces. This field must read the same in each instance of this register and for any value in MPAMCFG_PART_SEL.RIS. 0b0 This MSC supports two PARTID spaces. 0b1 This MSC supports four PARTID spaces. RO When MPAMF_IDR.EXT == '1' and FEAT_RME is implemented 41 41 41 Reserved, RES0. Otherwise HAS_ERR_MSI 40 40 0 Has support for MSI writes to signal MPAM error interrupts. These registers are implemented: MPAMF_ERR_MSI_ADDR_L, MPAMF_ERR_MSI_ADDR_H, MPAMF_ERR_MSI_ATTR, MPAMF_ERR_MSI_DATA, and MPAMF_ERR_MSI_MPAM. If MPAMF_IDR.HAS_ESR is 0, this bit must also be 0. 0b0 MPAMF_ERR_MSI_ADDR_L, MPAMF_ERR_MSI_ADDR_H, MPAMF_ERR_MSI_ATTR, MPAMF_ERR_MSI_DATA, and MPAMF_ERR_MSI_MPAM registers are not implemented. 0b1 MPAMF_ERR_MSI_ADDR_L, MPAMF_ERR_MSI_ADDR_H, MPAMF_ERR_MSI_ATTR, MPAMF_ERR_MSI_DATA, and MPAMF_ERR_MSI_MPAM are implemented and can be used to generate writes to signal error interrupts. RO When MPAMF_IDR.EXT == '1' 40 40 40 Reserved, RES0. Otherwise HAS_ESR 39 39 0 MPAMF_ESR is implemented. If an MSC cannot encounter any of the error conditions listed in MPAM MSC Errors of Arm® Memory System Resource Partitioning and Monitoring (MPAM) System Component Specification (ARM IHI 0099), both the MPAMF_ESR and MPAMF_ECR must be RAZ/WI. 0b0 MPAMF_ESR, MPAMF_ECR, and MPAM error handling are not implemented. 0b1 MPAMF_ESR, MPAMF_ECR, and MPAM error handling are implemented. RO When MPAMF_IDR.EXT == '1' 39 39 39 Reserved, RES0. Otherwise HAS_EXTD_ESR 38 38 0 MPAMF_ESR is 64 bits. When MPAMF_IDR.HAS_RIS and MPAMF_IDR.HAS_ESR, this field must be 1. 0b0 MPAMF_ESR is 32 bits. 0b1 MPAMF_ESR is 64 bits. RO When MPAMF_IDR.EXT == '1' 38 38 38 Reserved, RES0. Otherwise NO_IMPL_MSMON 37 37 0 MPAMF_IMPL_IDR defines no IMPLEMENTATION DEFINED resource monitors. If MPAMF_IDR.RIS is 1, this field indicates the presence of IMPLEMENTATION DEFINED resource monitors described in MPAMF_IMPL_IDR for the selected resource instance. 0b0 MPAMF_IMPL_IDR defines at least one IMPLEMENTATION DEFINED resource monitor. 0b1 MPAMF_IMPL_IDR does not define any IMPLEMENTATION DEFINED resource monitors. RO When MPAMF_IDR.EXT == '1' and MPAMF_IDR.HAS_IMPL_IDR == '1' 37 37 37 Reserved, RES0. Otherwise NO_IMPL_PART 36 36 0 MPAMF_IMPL_IDR defines no IMPLEMENTATION DEFINED resource controls. If MPAMF_IDR.RIS is 1, this field indicates the presence of IMPLEMENTATION DEFINED resource controls described in MPAMF_IMPL_IDR for the selected resource instance. 0b0 MPAMF_IMPL_IDR defines at least one IMPLEMENTATION DEFINED resource control. 0b1 MPAMF_IMPL_IDR does not define any IMPLEMENTATION DEFINED resource controls. RO When MPAMF_IDR.EXT == '1' and MPAMF_IDR.HAS_IMPL_IDR == '1' 36 36 36 Reserved, RES0. Otherwise 35 33 35:33 Reserved, RES0. HAS_RIS 32 32 0 Has resource instance selector. Indicates that MPAMCFG_PART_SEL contains the RIS field that selects a resource instance to control. 0b0 MPAMCFG_PART_SEL does not implement the MPAMCFG_PART_SEL.RIS field or multiple resource instance support. 0b1 MPAMCFG_PART_SEL implements the MPAMCFG_PART_SEL.RIS field and MPAM resource instance numbers up to and including MPAMF_IDR.RIS_MAX. RO When MPAMF_IDR.EXT == '1' 32 32 32 Reserved, RES0. Otherwise HAS_PARTID_NRW 31 31 31 Has PARTID Narrowing. 0b0 Does not have MPAMF_PARTID_NRW_IDR, MPAMCFG_INTPARTID, or intPARTID mapping support. 0b1 Supports the MPAMF_PARTID_NRW_IDR, MPAMCFG_INTPARTID registers. RO HAS_MSMON 30 30 30 Has resource Monitors. Indicates whether this MSC has MPAM resource monitors. 0b0 Does not support MPAM resource monitoring by groups or MPAMF_MSMON_IDR. 0b1 Supports resource monitoring by matching a combination of PARTID and PMG. See MPAMF_MSMON_IDR. RO HAS_IMPL_IDR 29 29 29 Has MPAMF_IMPL_IDR. Indicates whether this MSC has the IMPLEMENTATION SPECIFIC MPAM features register, MPAMF_IMPL_IDR. 0b0 Does not have MPAMF_IMPL_IDR. 0b1 Has MPAMF_IMPL_IDR. RO EXT 28 28 28 Extended MPAMF_IDR. 0b0 MPAMF_IDR has no defined bits in [63:32]. The register is effectively 32 bits. 0b1 MPAMF_IDR has bits defined in [63:32]. The register is 64 bits. RO HAS_PRI_PART 27 27 27 Has Priority Partitioning. Indicates that MPAM priority partitioning is implemented and MPAMF_PRI_IDR exists. If MPAMF_IDR.RIS is 1, this field indicates the presence of priority partitioning resource controls as described in MPAMF_PRI_IDR for the selected resource instance. 0b0 Does not support priority partitioning or have MPAMF_PRI_IDR. 0b1 Has priority partitioning and MPAMF_PRI_IDR. RO HAS_MBW_PART 26 26 26 Has Memory Bandwidth Partitioning. Indicates whether this MSC implements MPAM memory bandwidth partitioning and MPAMF_MBW_IDR. If MPAMF_IDR.RIS is 1, this field indicates the presence of memory bandwidth partitioning resource controls as described in MPAMF_MBW_IDR for the selected resource instance. 0b0 Does not support memory bandwidth partitioning or have MPAMF_MBW_IDR register. 0b1 Has MPAMF_MBW_IDR register. RO HAS_CPOR_PART 25 25 25 Has Cache Portion Partitioning. Indicates whether this MSC implements MPAM cache portion partitioning and MPAMF_CPOR_IDR. If MPAMF_IDR.RIS is 1, this field indicates the presence of cache portion partitioning resource controls as described in MPAMF_CPOR_IDR for the selected resource instance. 0b0 Does not support cache portion partitioning or have MPAMF_CPOR_IDR or MPAMCFG_CPBM<n> registers. 0b1 Has MPAMF_CPOR_IDR and MPAMCFG_CPBM<n> registers. RO HAS_CCAP_PART 24 24 24 Has Cache Capacity Partitioning. Indicates whether this MSC implements MPAM cache capacity partitioning and the MPAMF_CCAP_IDR and MPAMCFG_CMAX registers. If MPAMF_IDR.RIS is 1, this field indicates the presence of cache capacity partitioning resource controls as described in MPAMF_CCAP_IDR for the selected resource instance. 0b0 Does not support cache capacity partitioning or have MPAMF_CCAP_IDR and MPAMCFG_CMAX registers. 0b1 Has MPAMF_CCAP_IDR and MPAMCFG_CMAX registers. RO PMG_MAX 23 16 23:16 Maximum supported value of PMG. The value of this field is permitted to vary between the instances of MPAMF_IDR, each reporting the maximum supported PMG value in the PARTID space associated with that instance. In MPAMF_IDR_s, this field is permitted to report the maximum PMG value for the Non-secure PARTID space or for the Secure PARTID space. The maximum PMG value for the Secure PARTID space can be read from MPAMF_SIDR.PMG_MAX. This field has an IMPLEMENTATION DEFINED value. RO PARTID_MAX 15 0 15:0 Maximum supported value of PARTID. The value of this field is permitted to vary between the instances of MPAMF_IDR, each reporting the maximum supported PARTID value in the PARTID space associated with that instance. In MPAMF_IDR_s, this field is permitted to report the maximum PARTID value for the Non-secure PARTID space or for the Secure PARTID space. The maximum PARTID value for the Secure PARTID space can be read from MPAMF_SIDR.PARTID_MAX. This field has an IMPLEMENTATION DEFINED value. RO HAS_PARTID_NRW 31 31 31 Has PARTID Narrowing. 0b0 Does not have MPAMF_PARTID_NRW_IDR, MPAMCFG_INTPARTID, or intPARTID mapping support. 0b1 Supports the MPAMF_PARTID_NRW_IDR, MPAMCFG_INTPARTID registers. RO HAS_MSMON 30 30 30 Has resource Monitors. Indicates whether this MSC has MPAM resource monitors. 0b0 Does not support MPAM resource monitoring by groups or MPAMF_MSMON_IDR. 0b1 Supports resource monitoring by matching a combination of PARTID and PMG. See MPAMF_MSMON_IDR. RO HAS_IMPL_IDR 29 29 29 Has MPAMF_IMPL_IDR. Indicates whether this MSC has the IMPLEMENTATION SPECIFIC MPAM features register, MPAMF_IMPL_IDR. 0b0 Does not have MPAMF_IMPL_IDR. 0b1 Has MPAMF_IMPL_IDR. RO 28 28 28 Reserved, RES0. HAS_PRI_PART 27 27 27 Has Priority Partitioning. Indicates that MPAM priority partitioning is implemented and MPAMF_PRI_IDR exists. 0b0 Does not support priority partitioning or have MPAMF_PRI_IDR. 0b1 Has priority partitioning and MPAMF_PRI_IDR. RO HAS_MBW_PART 26 26 26 Has Memory Bandwidth Partitioning. Indicates whether this MSC implements MPAM memory bandwidth partitioning and MPAMF_MBW_IDR. 0b0 Does not support memory bandwidth partitioning or have MPAMF_MBW_IDR register. 0b1 Has MPAMF_MBW_IDR register. RO HAS_CPOR_PART 25 25 25 Has Cache Portion Partitioning. Indicates whether this MSC implements MPAM cache portion partitioning and MPAMF_CPOR_IDR. 0b0 Does not support cache portion partitioning or have MPAMF_CPOR_IDR or MPAMCFG_CPBM<n> registers. 0b1 Has MPAMF_CPOR_IDR and MPAMCFG_CPBM<n> registers. RO HAS_CCAP_PART 24 24 24 Has Cache Capacity Partitioning. Indicates whether this MSC implements MPAM cache capacity partitioning and the MPAMF_CCAP_IDR and MPAMCFG_CMAX registers. 0b0 Does not support cache capacity partitioning or have MPAMF_CCAP_IDR and MPAMCFG_CMAX registers. 0b1 Has MPAMF_CCAP_IDR and MPAMCFG_CMAX registers. RO PMG_MAX 23 16 23:16 Maximum supported value of PMG. The value of this field is permitted to vary between the instances of MPAMF_IDR, each reporting the maximum supported PMG value in the PARTID space associated with that instance. In MPAMF_IDR_s, this field is permitted to report the maximum PMG value for the Non-secure PARTID space or for the Secure PARTID space. The maximum PMG value for the Secure PARTID space can be read from MPAMF_SIDR.PMG_MAX. This field has an IMPLEMENTATION DEFINED value. RO PARTID_MAX 15 0 15:0 Maximum supported value of PARTID. The value of this field is permitted to vary between the instances of MPAMF_IDR, each reporting the maximum supported PARTID value in the PARTID space associated with that instance. In MPAMF_IDR_s, this field is permitted to report the maximum PARTID value for the Non-secure PARTID space or for the Secure PARTID space. The maximum PARTID value for the Secure PARTID space can be read from MPAMF_SIDR.PARTID_MAX. This field has an IMPLEMENTATION DEFINED value. RO When FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p1 is implemented This register is within the MPAM feature page memory frames. If FEAT_MPAM is implemented, the following statements apply: In a system that supports Secure and Non-secure memory maps, there must be both Secure and Non-secure MPAM feature pages. MPAMF_IDR must be readable from the Non-secure and Secure MPAM feature pages. MPAMF_IDR is permitted to have the same contents when read from the Secure or Non-secure MPAM feature pages unless the register contents are different for the different versions, when MPAMF_IDR_s is permitted to have either the same or different contents to MPAMF_IDR_ns. There must be separate registers in the Secure (MPAMF_IDR_s) and Non-secure (MPAMF_IDR_ns) MPAM feature pages. If both FEAT_MPAM and FEAT_RME are implemented, the following statements apply: In a system that supports Secure, Non-secure, Root, and Realm memory maps, there must be MPAM feature pages in all four address maps. MPAMF_IDR must be readable from the Non-secure, Secure, Root, and Realm MPAM feature pages. MPAMF_IDR is permitted to have the same contents when read from the Secure, Non-secure, Root, and Realm MPAM feature pages unless the register contents are different for the different versions: MPAMF_IDR_s is permitted to have either the same or different contents to MPAMF_IDR_ns, MPAMF_IDR_rt, or MPAMF_IDR_rl. MPAMF_IDR_ns is permitted to have either the same or different contents to MPAMF_IDR_rt or MPAMF_IDR_rl. MPAMF_IDR_rt is permitted to have either the same or different contents to MPAMF_IDR_rl. There must be separate registers in the Secure (MPAMF_IDR_s), Non-secure (MPAMF_IDR_ns), Root (MPAMF_IDR_rt), and Realm (MPAMF_IDR_rl) MPAM feature pages. If any one of these features is implemented: FEAT_MPAMv0p1 FEAT_MPAMv1p1 then, the following statements apply: When MPAMF_IDR.HAS_RIS is 1, MPAMF_IDR shows the configuration of MSC MPAM for the resource instance selected by MPAMCFG_PART_SEL.RIS. Fields that mention RIS in their field descriptions have values that track the implemented properties of the resource instance. Fields that do not mention RIS are constant across all resource instances. 2026-03-26 20:27:25 2026-03_rel