MPAMF_MBW_IDR MPAM Memory Bandwidth Partitioning Identification Register The power domain of MPAMF_MBW_IDR is IMPLEMENTATION DEFINED when (FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p0 is implemented) and MPAMF_IDR.HAS_MBW_PART == '1' MPAM MPAMF_BASE_s 0x0040 MPAMF_MBW_IDR_s When FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented RO MPAM MPAMF_BASE_ns 0x0040 MPAMF_MBW_IDR_ns When FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented RO MPAM MPAMF_BASE_rt 0x0040 MPAMF_MBW_IDR_rt When FEAT_RME is implemented and (FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented) RO MPAM MPAMF_BASE_rl 0x0040 MPAMF_MBW_IDR_rl When FEAT_RME is implemented and (FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented) RO Indicates which MPAM bandwidth partitioning features are present on this MSC. MPAM If MPAMF_IDR.HAS_RIS is 1, some fields in this register give information for the resource instance currently selected by MPAMCFG_PART_SEL.RIS. The description of every field affected by MPAMCFG_PART_SEL.RIS has information within the field description. If FEAT_MPAMv1p0 or FEAT_MPAMv0p1 is implemented, then the following statements apply: MPAMF_MBW_IDR_s indicates bandwidth partitioning features accessed from the Secure MPAM feature page. MPAMF_MBW_IDR_ns indicates bandwidth partitioning features accessed from the Non-secure MPAM feature page. If FEAT_RME is implemented, then the following statements also apply: MPAMF_MBW_IDR_rt indicates bandwidth partitioning features accessed from the Root MPAM feature page. MPAMF_MBW_IDR_rl indicates bandwidth partitioning features accessed from the Realm MPAM feature page. The power and reset domain of each MSC component is specific to that component. MPAMF_MBW_IDR is a 32-bit register. 31 29 31:29 Reserved, RES0. BWPBM_WD 28 16 28:16 Bandwidth portion bitmap width. The number of bandwidth portion bits in the MPAMCFG_MBW_PBM<n> register array. If MPAMF_MBW_IDR.HAS_PBM is 1, this field must contain a value from 1 to 4096, inclusive. Values greater than 32 require a group of 32-bit registers to access the BWPBM, up to 128 if BWPBM_WD is the largest value. If MPAMF_MBW_IDR.HAS_PBM is 0, this field must be ignored by software. If RIS is implemented, this field indicates the width of the memory bandwidth portion bitmap partitioning control for the resource instance selected by MPAMCFG_PART_SEL.RIS. This field has an IMPLEMENTATION DEFINED value. RO 15 15 15 Reserved, RES0. WINDWR 14 14 14 Indicates the bandwidth accounting period register is writable. 0b0 The bandwidth accounting period is readable from MPAMCFG_MBW_WINWD which might be fixed or vary due to clock rate reconfiguration of the memory channel or memory controller. 0b1 The bandwidth accounting width is readable and writable per partition in MPAMCFG_MBW_WINWD. RO HAS_PROP 13 13 13 Indicates that this MSC implements proportional stride bandwidth partitioning and the MPAMCFG_MBW_PROP register can be accessed. If RIS is implemented, this field indicates the presence of the memory bandwidth proportional stride partitioning control for the resource instance selected by MPAMCFG_PART_SEL.RIS. 0b0 There is no memory bandwidth proportional stride control and the MPAMCFG_MBW_PROP register is RES0. 0b1 The proportional stride memory bandwidth partitioning scheme is supported and the MPAMCFG_MBW_PROP register can be accessed. RO HAS_PBM 12 12 12 Indicates that bandwidth portion partitioning is implemented and the MPAMCFG_MBW_PBM<n> register array can be accessed. If RIS is implemented, this field indicates the presence of the memory bandwidth portion partitioning control for the resource instance selected by MPAMCFG_PART_SEL.RIS. 0b0 There is no memory bandwidth portion control and the MPAMCFG_MBW_PBM<n> is RES0. 0b1 The memory bandwidth portion allocation scheme exists and the MPAMCFG_MBW_PBM<n> register can be accessed. RO HAS_MAX 11 11 11 Indicates that this MSC implements maximum bandwidth partitioning and the MPAMCFG_MBW_MAX register can be accessed. If RIS is implemented, this field indicates the presence of the maximum bandwidth partitioning control for the resource instance selected by MPAMCFG_PART_SEL.RIS. 0b0 There is no maximum memory bandwidth control and the MPAMCFG_MBW_MAX register is RES0. 0b1 The maximum memory bandwidth allocation scheme is supported and the MPAMCFG_MBW_MAX register can be accessed. The MPAMF_MBW_IDR.MAX_LIM and MPAMCFG_MBW_MAX.HARDLIM fields indicate which limit behaviors are implemented and enabled. RO HAS_MIN 10 10 10 Indicates that this MSC implements minimum bandwidth partitioning and the MPAMCFG_MBW_MIN register can be accessed. If RIS is implemented, this field indicates the presence of the minimum bandwidth partitioning control for the resource instance selected by MPAMCFG_PART_SEL.RIS. 0b0 There is no minimum memory bandwidth control and the MPAMCFG_MBW_MIN register is RES0. 0b1 The minimum memory bandwidth allocation scheme is supported and the MPAMCFG_MBW_MIN register can be accessed. RO MAX_LIM 9 8 9:8 Implemented maximum bandwidth partitioning behaviors. If both soft limit and hard limit behaviors are implemented, MPAMCFG_MBW_MAX.HARDLIM selects which behavior is used. If RIS is implemented, this field indicates the implemented maximum bandwidth limit partitioning behaviors for the resource instance selected by MPAMCFG_PART_SEL.RIS. 0b00 Both soft limit and hard limit behaviors are implemented. 0b01 Soft limit behavior is implemented, hard limit behavior is not implemented. 0b10 Hard limit behavior is implemented, soft limit behavior is not implemented. When MPAMF_MBW_IDR.HAS_MAX != '1' RES0 7 6 7:6 Reserved, RES0. BWA_WD 5 0 5:0 Number of implemented bits in the bandwidth allocation fields: MIN, MAX, and STRIDE. See MPAMCFG_MBW_MIN, MPAMCFG_MBW_MAX, and MPAMCFG_MBW_PROP. In any of these bandwidth allocation fields exist, this field must have a value from 1 to 16, inclusive. Otherwise, it is permitted to be 0. If RIS is implemented, this field indicates the number of implemented bits in the bandwidth allocation control fields for the resource instance selected by MPAMCFG_PART_SEL.RIS. This field has an IMPLEMENTATION DEFINED value. RO If both FEAT_MPAM and FEAT_RME are implemented, the following statements apply: In a system that supports Secure, Non-secure, Root, and Realm memory maps, there must be MPAM feature pages in all four address maps. MPAMF_MBW_IDR must be readable from the Non-secure, Secure, Root, and Realm MPAM feature pages. MPAMF_MBW_IDR is permitted to have the same contents when read from the Secure, Non-secure, Root, and Realm MPAM feature pages unless the register contents are different for the different versions: MPAMF_MBW_IDR_s is permitted to have either the same or different contents to MPAMF_MBW_IDR_ns, MPAMF_MBW_IDR_rt, or MPAMF_MBW_IDR_rl. MPAMF_MBW_IDR_ns is permitted to have either the same or different contents to MPAMF_MBW_IDR_rt or MPAMF_MBW_IDR_rl. MPAMF_MBW_IDR_rt is permitted to have either the same or different contents to MPAMF_MBW_IDR_rl. There must be separate registers in the Secure (MPAMF_MBW_IDR_s), Non-secure (MPAMF_MBW_IDR_ns), Root (MPAMF_MBW_IDR_rt), and Realm (MPAMF_MBW_IDR_rl) MPAM feature pages. If any one of these features is implemented: FEAT_MPAMv0p1 FEAT_MPAMv1p1 then, the following statements apply: When MPAMF_IDR.HAS_RIS is 1, MPAMF_MBW_IDR shows the configuration of memory bandwidth partitioning for the bandwidth resource instance selected by MPAMCFG_PART_SEL.RIS. Fields that mention RIS in their field descriptions have values that track the implemented properties of the resource instance. Fields that do not mention RIS are constant across all resource instances. 2026-03-26 20:27:25 2026-03_rel