MPAMF_MSMON_IDR MPAM Resource Monitoring Identification Register The power domain of MPAMF_MSMON_IDR is IMPLEMENTATION DEFINED when FEAT_MPAM_MSC_MSMON is implemented MPAM MPAMF_BASE_s 0x0080 MPAMF_MSMON_IDR_s When FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented RO MPAM MPAMF_BASE_ns 0x0080 MPAMF_MSMON_IDR_ns When FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented RO MPAM MPAMF_BASE_rt 0x0080 MPAMF_MSMON_IDR_rt When FEAT_RME is implemented and (FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented) RO MPAM MPAMF_BASE_rl 0x0080 MPAMF_MSMON_IDR_rl When FEAT_RME is implemented and (FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented) RO Indicates which MPAM monitoring features are present on this MSC. MPAM If MPAMF_IDR.HAS_RIS is 1, fields that mention RIS must reflect the properties of the resource instance currently selected by MPAMCFG_PART_SEL.RIS. Fields that do not mention RIS are constant across all resource instances. If FEAT_MPAMv1p0 or FEAT_MPAMv0p1 is implemented, then the following statements apply: MPAMF_MSMON_IDR_s indicates Secure monitoring features. MPAMF_MSMON_IDR_ns indicates Non-secure monitoring features. If FEAT_RME is implemented, then the following statements also apply: MPAMF_MSMON_IDR_rt indicates Root monitoring features. MPAMF_MSMON_IDR_rl indicates Realm monitoring features. The power and reset domain of each MSC component is specific to that component. MPAMF_MSMON_IDR is a 32-bit register. HAS_LOCAL_CAPT_EVNT 31 31 31 Has local capture event generator. Indicates whether this MSC has the MPAM local capture event generator and the MSMON_CAPT_EVNT register. 0b0 Does not support MPAM local capture event generator or MSMON_CAPT_EVNT. 0b1 Supports the MPAM local capture event generator and the MSMON_CAPT_EVNT register. RO NO_HW_OFLW_INTR 30 30 0 Does not have hardwired MPAM monitor overflow interrupt. If this field is 0, the MSC supports generating a hardwired interrupt for monitor overflow events. If this field is 0 and the HAS_OFLW_MSI field in this register is 1, the MSC supports generating both hardwired interrupts and MSI writes to signal interrupts. 0b0 Supports generating a hardwired interrupt to signal MPAM monitor overflow. 0b1 No support for a hardwired interrupt to signal MPAM monitor overflow. RO When FEAT_MPAMv1p1 is implemented 30 30 30 Reserved, RES0. Otherwise HAS_OFLW_MSI 29 29 0 Has support for MSI writes to signal MPAM monitor overflow interrupts. These registers are implemented: MSMON_OFLOW_MSI_ADDR_L, MSMON_OFLOW_MSI_ADDR_H, MSMON_OFLOW_MSI_ATTR, MSMON_OFLOW_MSI_DATA and MSMON_OFLOW_MSI_MPAM. If MPAMF_MSMON_IDR.NO_HW_OFLW_INTR is 1 and this bit is 0, this MSC does not support monitor overflow interrupts. 0b0 MSMON_OFLOW_MSI_ADDR_L, MSMON_OFLOW_MSI_ADDR_H, MSMON_OFLOW_MSI_ATTR, MSMON_OFLOW_MSI_DATA and MSMON_OFLOW_MSI_MPAM registers are not implemented. 0b1 MSMON_OFLOW_MSI_ADDR_L, MSMON_OFLOW_MSI_ADDR_H, MSMON_OFLOW_MSI_ATTR, MSMON_OFLOW_MSI_DATA and MSMON_OFLOW_MSI_ATTR are implemented and can be used to generate writes to signal MPAM monitor overflow interrupts. RO When FEAT_MPAMv1p1 is implemented 29 29 29 Reserved, RES0. Otherwise HAS_OFLOW_SR 28 28 0 Has MPAM monitor overflow status register MSMON_OFLOW_SR. 0b0 Does not have MSMON_OFLOW_SR. 0b1 Supports MSMON_OFLOW_SR. RO When FEAT_MPAMv1p1 is implemented 28 28 28 Reserved, RES0. Otherwise HAS_TL_MONITORING 27 26 1:0 Indicates whether the monitor supports filtering based on ingress unstranslated MPAM information, translated egress MPAM information, or intermediate MPAM information. 0b00 The monitor filters on the intermediate MPAM information, after ingress translation and before egress translation, if implemented and enabled. 0b01 The monitor filters on the incoming untranslated MPAM information of the memory request, before ingress translation. When MPAMF_IDR.HAS_IN_TL == '1' 0b10 The monitor filters on the outgoing resulting MPAM information of the memory request after egress translation. When MPAMF_IDR.HAS_OUT_TL == '1' 0b11 Reserved. RO When FEAT_MPAM_MSC_DOMAINS is implemented 27 26 27:26 Reserved, RES0. Otherwise 25 19 25:19 Reserved, RES0. MSMON_CSA 18 18 18 Reports if the cache storage allocation (CSA) monitor is implemented. If MPAMF_IDR.HAS_RIS is 1, this field reports that the CSA monitor is implemented for the resource instance selected by MPAMCFG_PART_SEL.RIS. FEAT_MPAM_CSA implements the functionality identified by the value '1'. 0b0 The cache storage allocation (CSA) monitor is not implemented. 0b1 The cache storage allocation (CSA) monitor is implemented. RO MSMON_MBWU 17 17 17 Memory bandwidth usage monitoring. Indicates whether MPAM monitoring for Memory Bandwidth Usage by PARTID and PMG is implemented and whether the following bandwidth usage registers are accessible: MPAMF_MBWUMON_IDR, MSMON_CFG_MBWU_CTL, MSMON_CFG_MBWU_FLT, MSMON_MBWU. The optional MSMON_MBWU_CAPTURE. If MPAM v0.1 or MPAM v1.1 is implemented, the optional MSMON_MBWU_L and the optional MSMON_MBWU_L_CAPTURE. If RIS is implemented, this field indicates that memory bandwidth usage monitoring is implemented for the resource instance selected by MPAMCFG_PART_SEL.RIS as described in MPAMF_MBWUMON_IDR. 0b0 Does not have monitoring for memory bandwidth usage and does not use the bandwidth usage registers. 0b1 Has monitoring of memory bandwidth usage and uses the bandwidth usage registers. RO MSMON_CSU 16 16 16 Cache storage usage monitoring. Indicates whether MPAM monitoring of cache storage usage by PARTID and PMG is implemented and the following registers are accessible: MPAMF_CSUMON_IDR, MSMON_CFG_CSU_CTL, MSMON_CFG_CSU_FLT, MSMON_CSU. The optional MSMON_CSU_CAPTURE. If RIS is implemented, this field indicates that cache storage usage monitoring is implemented for the resource instance selected by MPAMCFG_PART_SEL.RIS as described in MPAMF_CSUMON_IDR. 0b0 Does not have monitoring for cache storage usage or the MPAMF_CSUMON_IDR, MSMON_CFG_CSU_CTL, MSMON_CFG_CSU_FLT, MSMON_CSU or MSMON_CSU_CAPTURE registers. 0b1 Has monitoring of cache storage usage and the MPAMF_CSUMON_IDR, MSMON_CFG_CSU_CTL, MSMON_CFG_CSU_FLT, MSMON_CSU and optional MSMON_CSU_CAPTURE registers. RO 15 0 15:0 Reserved, RES0. If both FEAT_MPAM and FEAT_RME are implemented, the following statements apply: In a system that supports Secure, Non-secure, Root, and Realm memory maps, there must be MPAM feature pages in all four address maps. MPAMF_MSMON_IDR must be readable from the Non-secure, Secure, Root, and Realm MPAM feature pages. MPAMF_MSMON_IDR is permitted to have the same contents when read from the Secure, Non-secure, Root, and Realm MPAM feature pages unless the register contents are different for the different versions: MPAMF_MSMON_IDR_s is permitted to have either the same or different contents to MPAMF_MSMON_IDR_ns, MPAMF_MSMON_IDR_rt, or MPAMF_MSMON_IDR_rl. MPAMF_MSMON_IDR_ns is permitted to have either the same or different contents to MPAMF_MSMON_IDR_rt or MPAMF_MSMON_IDR_rl. MPAMF_MSMON_IDR_rt is permitted to have either the same or different contents to MPAMF_MSMON_IDR_rl. There must be separate registers in the Secure (MPAMF_MSMON_IDR_s), Non-secure (MPAMF_MSMON_IDR_ns), Root (MPAMF_MSMON_IDR_rt), and Realm (MPAMF_MSMON_IDR_rl) MPAM feature pages. If any one of these features is implemented: FEAT_MPAMv0p1 FEAT_MPAMv1p1 then, the following statements apply: When MPAMF_IDR.HAS_RIS is 1, MPAMF_MSMON_IDR shows the configuration of memory system monitoring for the resource instance selected by MPAMCFG_PART_SEL.RIS. Fields that mention RIS in their field descriptions have values that track the implemented properties of the resource instance. Fields that do not mention RIS are constant across all resource instances. Access to MPAMF_MSMON_IDR is not affected by MSMON_CFG_MON_SEL.RIS. 2026-03-26 20:27:25 2026-03_rel