MSMON_MBWU_OFSR MPAM MBWU Monitor Overflow Status Register The power domain of MSMON_MBWU_OFSR is IMPLEMENTATION DEFINED when FEAT_MPAM_MSC_MSMON is implemented, MPAMF_MSMON_IDR.MSMON_MBWU == '1', and MPAMF_MBWUMON_IDR.HAS_OFSR == '1' MPAM MPAMF_BASE_s 0x0898 MSMON_MBWU_OFSR_s When FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented RO MPAM MPAMF_BASE_ns 0x0898 MSMON_MBWU_OFSR_ns When FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented RO MPAM MPAMF_BASE_rt 0x0898 MSMON_MBWU_OFSR_rt When FEAT_RME is implemented and (FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented) RO MPAM MPAMF_BASE_rl 0x0898 MSMON_MBWU_OFSR_rl When FEAT_RME is implemented and (FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented) RO MSMON_MBWU_OFSR is a 32-bit read-only register that shows bitmap of MBWU monitor instance overflow status for a contiguous group of 32 monitor instances. MPAM If FEAT_MPAMv0p1 or FEAT_MPAMv1p0 is implemented, the register is banked and the following statements apply: MSMON_MBWU_OFSR_s gives a bitmap of pending MBWU overflow status for 32 Secure MBWU monitor instances. MSMON_MBWU_OFSR_ns gives a bitmap of pending MBWU overflow status for 32 Non-secure MBWU monitor instances. If FEAT_RME is implemented, the following statements also apply: MSMON_MBWU_OFSR_rt gives a bitmap of pending MBWU overflow status for 32 Root MBWU monitor instances. MSMON_MBWU_OFSR_rl gives a bitmap of pending MBWU overflow status for 32 Realm MBWU monitor instances. The power and reset domain of each MSC component is specific to that component. MSMON_MBWU_OFSR is a 32-bit register. OFPND<i> 31 0 31:0 Overflow status bitmap for MBWU monitor instances. The RIS and the contiguous range of MBWU monitor instances are set in MSMON_CFG_MON_SEL. i of 0 corresponds to the MBWU monitor instance MSMON_CFG_MON_SEL.MON_SEL & 0xFFE0. After reading MSMON_OFLOW_SR to determine that an MBWU monitor instance has a pending overflow and which RIS values have pending overflows, an interrupt service routine could poll groups of 32 monitor instances in a RIS for pending monitors by reading this bitmap and incrementing MSMON_CFG_MON_SEL.MON_SEL by 32. A pending overflow may be in either the MSMON_CFG_MBWU_CTL.OFLOW_STATUS or MSMON_CFG_MBWU_CTL.OFLOW_STATUS_L field. 31 0 0b0 MBWU monitor instance (MSMON_CFG_MON_SEL.MON_SEL & 0xFFE0 + i) does not have a pending overflow. 0b1 MBWU monitor instance (MSMON_CFG_MON_SEL.MON_SEL & 0xFFE0 + i) has a pending overflow. If both FEAT_MPAM and FEAT_RME are implemented, the following statements apply: In a system that supports Secure, Non-secure, Root, and Realm memory maps, there must be MPAM feature pages in all four address maps: MSMON_MBWU_OFSR_s must only be accessible from the Secure MPAM feature page. MSMON_MBWU_OFSR_ns must only be accessible from the Non-secure MPAM feature page. MSMON_MBWU_OFSR_rt must only be accessible from the Root MPAM feature page. MSMON_MBWU_OFSR_rl must only be accessible from the Realm MPAM feature page. MSMON_MBWU_OFSR_s, MSMON_MBWU_OFSR_ns, MSMON_MBWU_OFSR_rt, and MSMON_MBWU_OFSR_rl must be separate registers: The Secure instance (MSMON_MBWU_OFSR_s) accesses the MBWU monitor overflow status bitmap used for Secure PARTIDs. The Non-secure instance (MSMON_MBWU_OFSR_ns) accesses the MBWU monitor overflow status bitmap used for Non-secure PARTIDs. The Root instance (MSMON_MBWU_OFSR_rt) accesses the MBWU monitor overflow status bitmap used for Root PARTIDs. The Realm instance (MSMON_MBWU_OFSR_rl) accesses the MBWU monitor overflow status bitmap used for Realm PARTIDs. 2026-03-26 20:27:25 2026-03_rel