MSMON_OFLOW_SR MPAM Monitor Overflow Status Register The power domain of MSMON_OFLOW_SR is IMPLEMENTATION DEFINED when FEAT_MPAM_MSC_MSMON is implemented and MPAMF_MSMON_IDR.HAS_OFLOW_SR == '1' MPAM MPAMF_BASE_s 0x08F0 MSMON_OFLOW_SR_s When FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented RO MPAM MPAMF_BASE_ns 0x08F0 MSMON_OFLOW_SR_ns When FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented RO MPAM MPAMF_BASE_rt 0x08F0 MSMON_OFLOW_SR_rt When FEAT_RME is implemented and (FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented) RO MPAM MPAMF_BASE_rl 0x08F0 MSMON_OFLOW_SR_rl When FEAT_RME is implemented and (FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented) RO MSMON_OFLOW_SR is a 32-bit read-only register that shows MPAM monitor overflow status for this MSC. MPAM If FEAT_MPAMv1p0 or FEAT_MPAMv0p1 is implemented, then the following statements apply: MSMON_OFLOW_SR_s gives the status of overflows of Secure MPAM monitors. MSMON_OFLOW_SR_ns gives the status of overflows of Non-secure MPAM monitors. If FEAT_RME is implemented, then the following statements also apply: MSMON_OFLOW_SR_rt gives the status of overflows of Root MPAM monitors. MSMON_OFLOW_SR_rl gives the status of overflows of Realm MPAM monitors. The power and reset domain of each MSC component is specific to that component. MSMON_OFLOW_SR is a 32-bit register. CSU_OFLOW_PND 31 31 31 At least one cache storage usage monitor has OFLOW_STATUS of 1 in MSMON_CFG_CSU_CTL. This field clears when MSMON_CFG_CSU_CTL.OFLOW_STATUS has been reset to 0 for all CSU monitor instances in this MSC. 0b0 There are no cache storage usage monitor instances where MSMON_CFG_CSU_CTL.OFLOW_STATUS is 1. 0b1 MSMON_CFG_CSU_CTL for at least one of the cache storage usage monitor instances has OFLOW_STATUS set to 1. MBWU_OFLOW_PND 30 30 30 At least one memory bandwidth usage monitor instance has OFLOW_STATUS or OFLOW_STATUS_L of 1 in MSMON_CFG_MBWU_CTL. This field clears when MSMON_CFG_MBWU_CTL.OFLOW_STATUS and MSMON_CFG_MBWU_CTL.OFLOW_STATUS_L have been reset to 0 for all MBWU monitor instances in this MSC. 0b0 There are no memory bandwidth usage monitor instances where MSMON_CFG_MBWU_CTL.OFLOW_STATUS is 1. 0b1 MSMON_CFG_MBWU_CTL for at least one of the memory bandwidth usage monitor instances has either OFLOW_STATUS or OFLOW_STATUS_L set to 1. CSA_OFLOW_PND 29 29 0 If MPAMF_CSAMON_IDR.HAS_LONG is 1, reports that MSMON_CFG_CSA_CTL.{OFLOW_STATUS,OFLOW_STATUS_L} are {1,x} or {x,1} for at least one cache storage allocation monitor instance. Otherwise, reports that MSMON_CFG_CSA_CTL.OFLOW_STATUS is 1 for at least one cache storage allocation monitor instance. If MPAMF_CSAMON_IDR.HAS_LONG is 1, the value of this field becomes 0 when MSMON_CFG_CSA_CTL.{OFLOW_STATUS,OFLOW_STATUS_L} are reset to {0,0} for all cache storage allocation monitor instances. Otherwise, the value of this field becomes 0 when MSMON_CFG_CSA_CTL.OFLOW_STATUS is reset to 0 for all cache storage allocation monitor instances. 0b0 If MPAMF_CSAMON_IDR.HAS_LONG is 1, then MSMON_CFG_CSA_CTL.{OFLOW_STATUS,OFLOW_STATUS_L} are {0,0} for all cache storage allocation monitor instances. Otherwise, MSMON_CFG_CSA_CTL.OFLOW_STATUS is 0 for all cache storage allocation monitor instances. 0b1 If MPAMF_CSAMON_IDR.HAS_LONG is 1, then MSMON_CFG_CSA_CTL.{OFLOW_STATUS,OFLOW_STATUS_L} are {1,x} or {x,1} for at least one cache storage allocation monitor instance. Otherwise, MSMON_CFG_CSA_CTL.OFLOW_STATUS is 1 for at least one cache storage allocation monitor instance. AU When FEAT_MPAM_CSA is implemented 29 29 29 Reserved, RES0. Otherwise 28 16 28:16 Reserved, RES0. RIS_PND<r> 15 0 15:0 Overflow status by RIS. Combined with the CSU_OFLOW_PND and MBWU_OFLOW_PND flags in this register, an interrupt service routine could poll only the monitor types indicated in monitors for the resource instances flagged in this field. Bit r is set when any monitor instance of any type in resource instance r has OFLOW_STATUS or OFLOW_STATUS_L set to 1. 15 0 0b0 RIS r has no unread overflows of any type of monitor. 0b1 RIS r has at least one unread overflow in at least one of the monitor types. This register is within the MPAM feature page memory frames. In a system that supports Secure, Non-secure, Root, and Realm memory maps, there must be MPAM feature pages in all four address maps: MSMON_OFLOW_SR_s must only be accessible from the Secure MPAM feature page. MSMON_OFLOW_SR_ns must only be accessible from the Non-secure MPAM feature page. MSMON_OFLOW_SR_rt must only be accessible from the Root MPAM feature page. MSMON_OFLOW_SR_rl must only be accessible from the Realm MPAM feature page. MSMON_OFLOW_SR_s, MSMON_OFLOW_SR_ns, MSMON_OFLOW_SR_rt, and MSMON_OFLOW_SR_rl must be separate registers: The Secure instance (MSMON_OFLOW_SR_s) accesses the monitor overflow status summary of Secure monitors. The Non-secure instance (MSMON_OFLOW_SR_ns) accesses the monitor overflow status summary of Non-secure monitors. The Root instance (MSMON_OFLOW_SR_rt) accesses the monitor overflow status summary of Root monitors. The Realm instance (MSMON_OFLOW_SR_rl) accesses the monitor overflow status summary of Realm monitors. 2026-03-26 20:27:25 2026-03_rel