TRBDEVARCH Trace Buffer Device Architecture Register TRBDEVARCH is in the Core power domain when FEAT_TRBE_EXT is implemented TRBE 0xFBC TRBDEVARCH When DoubleLockStatus() or !IsCorePowered() ERROR RO Provides discovery information for the component. Identification Registers TRBDEVARCH is a 32-bit register. ARCHITECT 31 21 31:21 Defines the architect of the component. For Trace Buffer, this is Arm Limited. Bits [31:28] are the JEP106 continuation code, 0b0100. Bits [27:21] are the JEP106 identification code, 0b0111011. Reads as 0b01000111011. RO PRESENT 20 20 20 DEVARCH present. Indicates that the TRBDEVARCH register is present. Reads as 0b1. RO REVISION 19 16 19:16 Revision. Defines the architecture revision of the component. All other values are reserved. FEAT_TRBE implements the functionality identified by the value 0b0000. FEAT_TRBEv1p1 implements the functionality identified by the value 0b0001. From Armv9.6, the value 0b0000 is not permitted. 0b0000 First revision. 0b0001 As 0b0000, and adds: If EL2 and FEAT_FGT are implemented, a fine-grained trap on the TSB CSYNC instruction. If EL2 is implemented, an EL2 control to override TRBLIMITR_EL1.nVM. The TRBE Profiling exception extension, FEAT_TRBE_EXC. RO ARCHVER 15 12 15:12 Architecture Version. Defines the architecture version of the component. All other values are reserved. TRBDEVARCH.ARCHVER and TRBDEVARCH.ARCHPART are also defined as a single field, TRBDEVARCH.ARCHID, so that TRBDEVARCH.ARCHVER is TRBDEVARCH.ARCHID[15:12]. 0b0000 Trace Buffer Extension version 1. RO ARCHPART 11 0 11:0 Architecture Part. Defines the architecture of the component. TRBDEVARCH.ARCHVER and TRBDEVARCH.ARCHPART are also defined as a single field, TRBDEVARCH.ARCHID, so that TRBDEVARCH.ARCHPART is TRBDEVARCH.ARCHID[11:0]. 0xA18 Armv9-A Trace Buffer Extension. RO 2026-03-26 20:27:25 2026-03_rel