TRBIDR_EL1 Trace Buffer ID Register TRBIDR_EL1 is in the Core power domain when FEAT_TRBE_EXT is implemented TRBE 0x030 TRBIDR_EL1 When DoubleLockStatus(), or !IsCorePowered(), or OSLockStatus(), or !AllowExternalTraceBufferAccess(addrdesc) ERROR RO TRBIDR_EL1 Architectural AArch64 63 0 63 0 63 0 63 0 Describes constraints on using the Trace Buffer Unit to an external debugger. TRBE TRBIDR_EL1 is a 64-bit register. 63 48 63:48 Reserved, RES0. MaxBuffSize 47 32 47:32 Maximum supported trace buffer size. Reserved for software use. The only permitted value is 0x0000, indicating there is no limit to the maximum buffer size. Reads as 0x0000. RO 31 16 31:16 Reserved, RES0. MPAM 15 12 3:0 FEAT_MPAMv0p1 or FEAT_MPAMv1p0 extensions. Indicates Memory Partitioning and Monitoring (MPAM) support in the Trace Buffer Unit when using External mode. When FEAT_MPAMv0p1 and FEAT_MPAMv1p0 are not implemented by the PE, the only permitted value is 0b0000. When either FEAT_MPAMv0p1 or FEAT_MPAMv1p0 is implemented by the PE, the value 0b0000 is not permitted. FEAT_TRBE_MPAM implements the functionality identified by the value 0b0010. 0b0000 FEAT_MPAMv0p1 and FEAT_MPAMv1p0 are not implemented by the PE. 0b0001 FEAT_MPAMv0p1 or FEAT_MPAMv1p0 is implemented by the Trace Buffer Unit, using Default physical PARTID and PMG values in External mode. 0b0010 Trace Buffer MPAM extensions implemented, using FEAT_MPAMv0p1 or FEAT_MPAMv1p0. RO When FEAT_TRBE_EXT is implemented 15 12 15:12 Reserved, RES0. Otherwise EA 11 8 11:8 External Abort handling. Describes how the PE manages External aborts on writes made by the Trace Buffer Unit to the trace buffer. All other values are reserved. From Armv9.3, the value 0b0000 is not permitted. The behavior described by this field does not apply for External aborts on a translation table walk, translation table update, or GPT walk made by the Trace Buffer Unit that are reported as MMU faults using TRBSR_ELx. For more information, see 'External aborts'. 0b0000 Not described. 0b0001 The PE ignores External aborts on writes made by the Trace Buffer Unit. 0b0010 An External abort on a write made by the Trace Buffer Unit generates an asynchronous SError exception at the PE. RO AddrMode 7 6 7:6 This field reads as an UNKNOWN value. F 5 5 5 Flag updates. Describes how address translations performed by the Trace Buffer Unit manage the Access flag and dirty state. If hardware management of the Access flag is disabled for a stage of translation, an access to a Page or Block with the Access flag bit not set in the descriptor will generate an Access Flag fault. If hardware management of the dirty state is disabled for a stage of translation, an access to a Page or Block will ignore the Dirty Bit Modifier in the descriptor and might generate a Permission fault, depending on the values of the access permission bits in the descriptor. From Armv9.3, the value 0 is not permitted. 0b0 Hardware management of the Access flag and dirty state for accesses made by the Trace Buffer Unit is always disabled for all translation stages. 0b1 Hardware management of the Access flag and dirty state for accesses made by the Trace Buffer Unit is controlled in the same way as explicit memory accesses in the trace buffer owning translation regime. RO P 4 4 4 This field reads as an UNKNOWN value. Align 3 0 3:0 Defines the minimum alignment constraint for writes to TRBPTR_EL1 and TRBTRG_EL1. All other values are reserved. 0b0000 Byte. 0b0001 Halfword. 0b0010 Word. 0b0011 Doubleword. 0b0100 16 bytes. 0b0101 32 bytes. 0b0110 64 bytes. 0b0111 128 bytes. 0b1000 256 bytes. 0b1001 512 bytes. 0b1010 1KB. 0b1011 2KB. RO 2026-03-26 20:27:25 2026-03_rel