TRBITCTRL Integration Mode Control Register TRBITCTRL is in the Core power domain when FEAT_TRBE_EXT is implemented TRBE 0xF00 TRBITCTRL When DoubleLockStatus(), or !IsCorePowered(), or OSLockStatus(), or !AllowExternalTraceBufferAccess(addrdesc) ERROR RW A component can use TRBITCTRL to dynamically switch between functional mode and integration mode. In integration mode, topology detection is enabled. After switching to integration mode and performing integration tests or topology detection, reset the system to ensure correct behavior of CoreSight and other connected system components. For additional information, see the CoreSight Architecture Specification. TRBE TRBITCTRL is a 32-bit register. 31 1 31:1 Reserved, RES0. IME 0 0 0 Integration Mode Enable. 0b0 Component functional mode. 0b1 Component integration mode. Support for topology detection and integration testing is enabled. AU When topology detection or integration functionality is implemented 0 0 0 Reserved, RES0. Otherwise The PE might ignore a write to TRBITCTRL if any of the following apply: TRBLIMITR_EL1.E == 1 and Trace Buffer Unit is using Self-hosted mode. TRBLIMITR_EL1.XE == 1 and the Trace Buffer Unit is using External mode. 2026-03-26 20:27:25 2026-03_rel