TRBLIMITR_EL1 Trace Buffer Limit Address Register TRBLIMITR_EL1 is in the Core power domain when FEAT_TRBE_EXT is implemented TRBE 0x010 TRBLIMITR_EL1 When DoubleLockStatus(), or !IsCorePowered(), or OSLockStatus(), or !AllowExternalTraceBufferAccess(addrdesc) ERROR RW TRBLIMITR_EL1 Architectural AArch64 63 0 63 0 63 0 63 0 Defines the top address for the trace buffer, and controls the trace buffer modes and enable. TRBE TRBLIMITR_EL1 is a 64-bit register. LIMIT 63 12 63:12 Trace buffer Limit pointer address. (TRBLIMITR_EL1.LIMIT << 12) is the address of the last byte in the trace buffer plus one. Bits [11:0] of the Limit pointer address are always zero. If the smallest implemented translation granule is not 4KB, then TRBLIMITR_EL1[N-1:12] are RES0, where N is the IMPLEMENTATION DEFINED value Log₂(smallest implemented translation granule). AU 11 7 11:7 Reserved, RES0. XE 6 6 6 Trace Buffer Unit External mode enable. Controls whether the Trace Buffer Unit is enabled when SelfHostedTraceEnabled() == FALSE. If SelfHostedTraceEnabled() == TRUE, then TRBLIMITR_EL1.E controls whether the Trace Buffer Unit is enabled. All output is discarded by the Trace Buffer Unit when the Trace Buffer Unit is disabled. 0b0 Trace Buffer Unit is not enabled by this control. 0b1 If SelfHostedTraceEnabled() is FALSE, the Trace Buffer Unit is enabled. '0' nVM 5 5 5 Address mode. If SelfHostedTraceEnabled() == FALSE, then the PE ignores the value of this field and the trace buffer pointers are always physical addresses. 0b0 The trace buffer pointers are virtual addresses. 0b1 The trace buffer pointers are: Physical address in the owning security state if the owning translation regime has no stage 2 translation. Intermediate physical addresses in the owning security state if the owning translation regime has stage 2 translations. AU When !SelfHostedTraceEnabled() RES1 RW TM 4 3 4:3 Trigger mode. All other values are reserved. 0b00 Stop on trigger. Flush trace, then stop collection and set TRBSR_EL1.IRQ to 1 on Trigger Event. 0b01 IRQ on trigger. Continue collection and set TRBSR_EL1.IRQ to 1 on Trigger Event. 0b11 Ignore trigger. Continue collection and leave TRBSR_EL1.IRQ unchanged on Trigger Event. AU FM 2 1 2:1 Trace buffer mode. All other values are reserved. 0b00 Fill mode. Stop collection and set TRBSR_EL1.IRQ to 1 on current write pointer wrap. 0b01 Wrap mode. Continue collection and set TRBSR_EL1.IRQ to 1 on current write pointer wrap. 0b11 Circular Buffer mode. Continue collection and leave TRBSR_EL1.IRQ unchanged on current write pointer wrap. AU E 0 0 0 Trace Buffer Unit enable. Controls whether the Trace Buffer Unit is enabled when SelfHostedTraceEnabled() == TRUE. If FEAT_TRBE_EXT is implemented and SelfHostedTraceEnabled() == FALSE, then TRBLIMITR_EL1.XE controls whether the Trace Buffer Unit is enabled. If FEAT_TRBE_EXT is not implemented, then the Trace Buffer Unit is disabled when SelfHostedTraceEnabled() == FALSE. All output is discarded by the Trace Buffer Unit when the Trace Buffer Unit is disabled. 0b0 Trace Buffer Unit is not enabled by this control. 0b1 If SelfHostedTraceEnabled() is TRUE, the Trace Buffer Unit is enabled. '0' The PE might ignore a write to TRBLIMITR_EL1, other than a write that modifies TRBLIMITR_EL1.E or TRBLIMITR_EL1.XE as appropriate, if any of the following apply: TRBLIMITR_EL1.E is 1 and the Trace Buffer Unit is using Self-hosted mode. TRBLIMITR_EL1.XE is 1 and the Trace Buffer Unit is using External mode. 2026-03-26 20:27:25 2026-03_rel