TRBPTR_EL1 Trace Buffer Write Pointer Register TRBPTR_EL1 is in the Core power domain when FEAT_TRBE_EXT is implemented TRBE 0x008 TRBPTR_EL1 When DoubleLockStatus(), or !IsCorePowered(), or OSLockStatus(), or !AllowExternalTraceBufferAccess(addrdesc) ERROR RW TRBPTR_EL1 Architectural AArch64 63 0 63 0 63 0 63 0 Defines the current write pointer for the trace buffer. TRBE TRBPTR_EL1 is a 64-bit register. PTR 63 0 63:0 Trace Buffer current write pointer address. Defines the virtual address of the next entry to be written to the trace buffer. If TRBIDR_EL1.Align is not zero, then it is IMPLEMENTATION DEFINED whether bits [M-1:0] are RES0 or read/write, where M is an integer between 1 and TRBIDR_EL1.Align inclusive. The architecture places restrictions on the values that software can write to the pointer. For more information see 'Restrictions on Programming the Trace Buffer Unit'. AU The PE might ignore a write to TRBPTR_EL1 if any of the following apply: TRBLIMITR_EL1.E is 1 and the Trace Buffer Unit is using Self-hosted mode. TRBLIMITR_EL1.XE is 1 and the Trace Buffer Unit is using External mode. 2026-03-26 20:27:25 2026-03_rel