TRCACVR<n> Trace Address Comparator Value Register <n> when FEAT_ETE is implemented, FEAT_TRC_EXT is implemented, and UInt(TRCIDR4.NUMACPAIRS) * 2 > n 0 15 ETE 0x400 + (8 * n) TRCACVR<n> When OSLockStatus(), or !AllowExternalTraceAccess(addrdesc), or !IsTraceCorePowered() ERROR RW TRCACVR<n> Architectural AArch64 63 0 63 0 63 0 63 0 Contains the address value. Trace TRCACVR<n> is a 64-bit register. ADDRESS 63 0 63:0 Address Value. The Address Comparators can support implementations that use multiple address widths. When the trace unit compares the ADDRESS field with an address that has a width less than this field, then the address must be zero-extended to the ADDRESS field width. The trace unit then compares all implemented bits. For example, in a system that supports both 32-bit and 64-bit addresses, when the PE is in AArch32 state the comparator must zero-extend the 32-bit address and compare against the full 64 bits that are stored in TRCACVR<n>.ADDRESS. This requires that the trace analyzer always programs all implemented bits of TRCACVR<n>.ADDRESS. The result of writing a value other than all zeros or all ones to ADDRESS at bits[63:P] is an UNKNOWN value, where P is defined as: 56, when FEAT_LVA3 is implemented. 52, when FEAT_LVA is implemented. 48, otherwise. The result of writing a value of all zeros or all ones to ADDRESS at bits[63:P] is the written value, and a read of the register returns the written value. AU Must be programmed if any of the following are true: TRCBBCTLR.RANGE[n/2] == 1. TRCRSCTLR<a>.GROUP == 0b0100 and TRCRSCTLR<a>.SAC[n] == 1. TRCRSCTLR<a>.GROUP == 0b0101 and TRCRSCTLR<a>.ARC[n/2] == 1. TRCVIIECTLR.EXCLUDE[n/2] == 1. TRCVIIECTLR.INCLUDE[n/2] == 1. TRCVISSCTLR.START[n] == 1. TRCVISSCTLR.STOP[n] == 1. TRCSSCCR<a>.ARC[n/2] == 1. TRCSSCCR<a>.SAC[n] == 1. TRCQCTLR.RANGE[n/2] == 1. Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state. 2026-03-26 20:27:25 2026-03_rel