<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
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<?xml-stylesheet href="one_register.xsl" type="text/xsl" ?>







<register_page>
  <registers>
  
    <register is_register="True" is_internal="False" is_stub_entry="False">
      <reg_short_name>TRCCIDCCTLR1</reg_short_name>
        
        <reg_long_name>Trace Context Identifier Comparator Control Register 1</reg_long_name>



      
            <reg_condition otherwise="RES0">when FEAT_ETE is implemented, FEAT_TRC_EXT is implemented, UInt(TRCIDR4.NUMCIDC) &gt; 0x4, and UInt(TRCIDR2.CIDSIZE) &gt; 0</reg_condition>
      

    
  <reg_address
      external_access="True"
    mem_map_access="True"
      power_domain="None"
  >
    <reg_component>ETE</reg_component>
    <reg_offset><hexnumber>0x684</hexnumber></reg_offset>
    <reg_instance>TRCCIDCCTLR1</reg_instance>
    <reg_access>
      
        
      <reg_access_state>
          <reg_access_level>When OSLockStatus(), or !AllowExternalTraceAccess(addrdesc), or !IsTraceCorePowered()</reg_access_level>
          <reg_access_type>ERROR</reg_access_type>
      </reg_access_state>
        
      <reg_access_state>
          <reg_access_type>RW</reg_access_type>
      </reg_access_state>
    </reg_access>
</reg_address>



          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        



    
      
      <reg_mapping>
        
  

    

  

    <mapped_name filename="AArch64-trccidcctlr1.xml">TRCCIDCCTLR1</mapped_name>
  <mapped_type>Architectural</mapped_type>
      <mapped_execution_state>AArch64</mapped_execution_state>
    <mapped_from_startbit>31</mapped_from_startbit>
    <mapped_from_endbit>0</mapped_from_endbit>
    <mapped_to_startbit>31</mapped_to_startbit>
    <mapped_to_endbit>0</mapped_to_endbit>
    <mapped_from_rangeset output="31:0">
      <range>
        <msb>31</msb>
        <lsb>0</lsb>
      </range>
    </mapped_from_rangeset>
    <mapped_to_rangeset output="31:0">
      <range>
        <msb>31</msb>
        <lsb>0</lsb>
      </range>
    </mapped_to_rangeset>

      </reg_mapping>

      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>Contains Context identifier mask values for the <register_link state="ext" id="ext-trccidcvrn.xml">TRCCIDCVR&lt;n&gt;</register_link> registers, for n = 4 to 7.</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
          <reg_group>Trace</reg_group>
      </reg_groups>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>TRCCIDCCTLR1 is a 32-bit register.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="32">
  <text_before_fields/>
  <field id="fieldset_0-31_24-1" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" reserved_type="RES0">
    <field_name>COMP7[&lt;m&gt;]</field_name>
    <field_msb>31</field_msb>
    <field_lsb>24</field_lsb>
    <rel_range>7:0</rel_range>
    <field_description order="before">
      <para>TRCCIDCVR7 mask control. Specifies the mask value that the trace unit applies to TRCCIDCVR7. Each bit in this field corresponds to a byte in TRCCIDCVR7.</para>
    </field_description>
    <field_array_indexes index_variable="m" element_size="1" range_specifier="m+24">
      <field_array_index>
        <field_array_start>7</field_array_start>
        <field_array_end>0</field_array_end>
      </field_array_index>
    </field_array_indexes>
    <field_values impdef="False">
      <field_value_instance>
        <field_value>0b0</field_value>
        <field_value_description>
          <para>The trace unit includes TRCCIDCVR7[(m×8+7):(m×8)] when it performs the Context identifier comparison.</para>
        </field_value_description>
      </field_value_instance>
      <field_value_instance>
        <field_value>0b1</field_value>
        <field_value_description>
          <para>The trace unit ignores TRCCIDCVR7[(m×8+7):(m×8)] when it performs the Context identifier comparison.</para>
        </field_value_description>
      </field_value_instance>
    </field_values>
    <field_resets>
      <field_reset reset_type="Trace unit">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
    <field_access>
      <field_access_state>
        <field_access_level>When m &gt;= UInt(TRCIDR2.CIDSIZE)</field_access_level>
        <field_access_type>
          <arm-defined-word>RES0</arm-defined-word>
        </field_access_type>
      </field_access_state>
      <field_access_state>
        <field_access_type>RW</field_access_type>
      </field_access_state>
    </field_access>
    <fields_condition>When UInt(TRCIDR4.NUMCIDC) &gt; 7</fields_condition>
  </field>
  <field id="fieldset_0-31_24-2" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>31</field_msb>
    <field_lsb>24</field_lsb>
    <rel_range>31:24</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
    <fields_condition>Otherwise</fields_condition>
  </field>
  <field id="fieldset_0-23_16-1" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" reserved_type="RES0">
    <field_name>COMP6[&lt;m&gt;]</field_name>
    <field_msb>23</field_msb>
    <field_lsb>16</field_lsb>
    <rel_range>7:0</rel_range>
    <field_description order="before">
      <para>TRCCIDCVR6 mask control. Specifies the mask value that the trace unit applies to TRCCIDCVR6. Each bit in this field corresponds to a byte in TRCCIDCVR6.</para>
    </field_description>
    <field_array_indexes index_variable="m" element_size="1" range_specifier="m+16">
      <field_array_index>
        <field_array_start>7</field_array_start>
        <field_array_end>0</field_array_end>
      </field_array_index>
    </field_array_indexes>
    <field_values impdef="False">
      <field_value_instance>
        <field_value>0b0</field_value>
        <field_value_description>
          <para>The trace unit includes TRCCIDCVR6[(m×8+7):(m×8)] when it performs the Context identifier comparison.</para>
        </field_value_description>
      </field_value_instance>
      <field_value_instance>
        <field_value>0b1</field_value>
        <field_value_description>
          <para>The trace unit ignores TRCCIDCVR6[(m×8+7):(m×8)] when it performs the Context identifier comparison.</para>
        </field_value_description>
      </field_value_instance>
    </field_values>
    <field_resets>
      <field_reset reset_type="Trace unit">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
    <field_access>
      <field_access_state>
        <field_access_level>When m &gt;= UInt(TRCIDR2.CIDSIZE)</field_access_level>
        <field_access_type>
          <arm-defined-word>RES0</arm-defined-word>
        </field_access_type>
      </field_access_state>
      <field_access_state>
        <field_access_type>RW</field_access_type>
      </field_access_state>
    </field_access>
    <fields_condition>When UInt(TRCIDR4.NUMCIDC) &gt; 6</fields_condition>
  </field>
  <field id="fieldset_0-23_16-2" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>23</field_msb>
    <field_lsb>16</field_lsb>
    <rel_range>23:16</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
    <fields_condition>Otherwise</fields_condition>
  </field>
  <field id="fieldset_0-15_8-1" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" reserved_type="RES0">
    <field_name>COMP5[&lt;m&gt;]</field_name>
    <field_msb>15</field_msb>
    <field_lsb>8</field_lsb>
    <rel_range>7:0</rel_range>
    <field_description order="before">
      <para>TRCCIDCVR5 mask control. Specifies the mask value that the trace unit applies to TRCCIDCVR5. Each bit in this field corresponds to a byte in TRCCIDCVR5.</para>
    </field_description>
    <field_array_indexes index_variable="m" element_size="1" range_specifier="m+8">
      <field_array_index>
        <field_array_start>7</field_array_start>
        <field_array_end>0</field_array_end>
      </field_array_index>
    </field_array_indexes>
    <field_values impdef="False">
      <field_value_instance>
        <field_value>0b0</field_value>
        <field_value_description>
          <para>The trace unit includes TRCCIDCVR5[(m×8+7):(m×8)] when it performs the Context identifier comparison.</para>
        </field_value_description>
      </field_value_instance>
      <field_value_instance>
        <field_value>0b1</field_value>
        <field_value_description>
          <para>The trace unit ignores TRCCIDCVR5[(m×8+7):(m×8)] when it performs the Context identifier comparison.</para>
        </field_value_description>
      </field_value_instance>
    </field_values>
    <field_resets>
      <field_reset reset_type="Trace unit">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
    <field_access>
      <field_access_state>
        <field_access_level>When m &gt;= UInt(TRCIDR2.CIDSIZE)</field_access_level>
        <field_access_type>
          <arm-defined-word>RES0</arm-defined-word>
        </field_access_type>
      </field_access_state>
      <field_access_state>
        <field_access_type>RW</field_access_type>
      </field_access_state>
    </field_access>
    <fields_condition>When UInt(TRCIDR4.NUMCIDC) &gt; 5</fields_condition>
  </field>
  <field id="fieldset_0-15_8-2" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>15</field_msb>
    <field_lsb>8</field_lsb>
    <rel_range>15:8</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
    <fields_condition>Otherwise</fields_condition>
  </field>
  <field id="fieldset_0-7_0-1" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" reserved_type="RES0">
    <field_name>COMP4[&lt;m&gt;]</field_name>
    <field_msb>7</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>7:0</rel_range>
    <field_description order="before">
      <para>TRCCIDCVR4 mask control. Specifies the mask value that the trace unit applies to TRCCIDCVR4. Each bit in this field corresponds to a byte in TRCCIDCVR4.</para>
    </field_description>
    <field_array_indexes index_variable="m" element_size="1" range_specifier="m">
      <field_array_index>
        <field_array_start>7</field_array_start>
        <field_array_end>0</field_array_end>
      </field_array_index>
    </field_array_indexes>
    <field_values impdef="False">
      <field_value_instance>
        <field_value>0b0</field_value>
        <field_value_description>
          <para>The trace unit includes TRCCIDCVR4[(m×8+7):(m×8)] when it performs the Context identifier comparison.</para>
        </field_value_description>
      </field_value_instance>
      <field_value_instance>
        <field_value>0b1</field_value>
        <field_value_description>
          <para>The trace unit ignores TRCCIDCVR4[(m×8+7):(m×8)] when it performs the Context identifier comparison.</para>
        </field_value_description>
      </field_value_instance>
    </field_values>
    <field_resets>
      <field_reset reset_type="Trace unit">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
    <field_access>
      <field_access_state>
        <field_access_level>When m &gt;= UInt(TRCIDR2.CIDSIZE)</field_access_level>
        <field_access_type>
          <arm-defined-word>RES0</arm-defined-word>
        </field_access_type>
      </field_access_state>
      <field_access_state>
        <field_access_type>RW</field_access_type>
      </field_access_state>
    </field_access>
    <fields_condition>When UInt(TRCIDR4.NUMCIDC) &gt; 4</fields_condition>
  </field>
  <field id="fieldset_0-7_0-2" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>7</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>7:0</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
    <fields_condition>Otherwise</fields_condition>
  </field>
  <text_after_fields/>
</fields>




<reg_fieldset length="32">
  <fieldat id="fieldset_0-31_24-1" label="COMP7[7]" msb="31" lsb="31"/>
  <fieldat id="fieldset_0-31_24-1" label="COMP7[6]" msb="30" lsb="30"/>
  <fieldat id="fieldset_0-31_24-1" label="COMP7[5]" msb="29" lsb="29"/>
  <fieldat id="fieldset_0-31_24-1" label="COMP7[4]" msb="28" lsb="28"/>
  <fieldat id="fieldset_0-31_24-1" label="COMP7[3]" msb="27" lsb="27"/>
  <fieldat id="fieldset_0-31_24-1" label="COMP7[2]" msb="26" lsb="26"/>
  <fieldat id="fieldset_0-31_24-1" label="COMP7[1]" msb="25" lsb="25"/>
  <fieldat id="fieldset_0-31_24-1" label="COMP7[0]" msb="24" lsb="24"/>
  <fieldat id="fieldset_0-23_16-1" label="COMP6[7]" msb="23" lsb="23"/>
  <fieldat id="fieldset_0-23_16-1" label="COMP6[6]" msb="22" lsb="22"/>
  <fieldat id="fieldset_0-23_16-1" label="COMP6[5]" msb="21" lsb="21"/>
  <fieldat id="fieldset_0-23_16-1" label="COMP6[4]" msb="20" lsb="20"/>
  <fieldat id="fieldset_0-23_16-1" label="COMP6[3]" msb="19" lsb="19"/>
  <fieldat id="fieldset_0-23_16-1" label="COMP6[2]" msb="18" lsb="18"/>
  <fieldat id="fieldset_0-23_16-1" label="COMP6[1]" msb="17" lsb="17"/>
  <fieldat id="fieldset_0-23_16-1" label="COMP6[0]" msb="16" lsb="16"/>
  <fieldat id="fieldset_0-15_8-1" label="COMP5[7]" msb="15" lsb="15"/>
  <fieldat id="fieldset_0-15_8-1" label="COMP5[6]" msb="14" lsb="14"/>
  <fieldat id="fieldset_0-15_8-1" label="COMP5[5]" msb="13" lsb="13"/>
  <fieldat id="fieldset_0-15_8-1" label="COMP5[4]" msb="12" lsb="12"/>
  <fieldat id="fieldset_0-15_8-1" label="COMP5[3]" msb="11" lsb="11"/>
  <fieldat id="fieldset_0-15_8-1" label="COMP5[2]" msb="10" lsb="10"/>
  <fieldat id="fieldset_0-15_8-1" label="COMP5[1]" msb="9" lsb="9"/>
  <fieldat id="fieldset_0-15_8-1" label="COMP5[0]" msb="8" lsb="8"/>
  <fieldat id="fieldset_0-7_0-1" label="COMP4[7]" msb="7" lsb="7"/>
  <fieldat id="fieldset_0-7_0-1" label="COMP4[6]" msb="6" lsb="6"/>
  <fieldat id="fieldset_0-7_0-1" label="COMP4[5]" msb="5" lsb="5"/>
  <fieldat id="fieldset_0-7_0-1" label="COMP4[4]" msb="4" lsb="4"/>
  <fieldat id="fieldset_0-7_0-1" label="COMP4[3]" msb="3" lsb="3"/>
  <fieldat id="fieldset_0-7_0-1" label="COMP4[2]" msb="2" lsb="2"/>
  <fieldat id="fieldset_0-7_0-1" label="COMP4[1]" msb="1" lsb="1"/>
  <fieldat id="fieldset_0-7_0-1" label="COMP4[0]" msb="0" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>

      <access_mechanisms>
          


  
    
      <access_permission_text>
        <para>If software uses the <register_link state="ext" id="ext-trccidcvrn.xml">TRCCIDCVR&lt;n&gt;</register_link> registers, for n = 4 to 7, then it must program this register.</para>

      </access_permission_text>
      <access_permission_text>
        <para>If software sets a mask bit to 1 then it must program the relevant byte in <register_link state="ext" id="ext-trccidcvrn.xml">TRCCIDCVR&lt;n&gt;</register_link> to <hexnumber>0x00</hexnumber>.</para>

      </access_permission_text>
      <access_permission_text>
        <para>If any bit is 1 and the relevant byte in <register_link state="ext" id="ext-trccidcvrn.xml">TRCCIDCVR&lt;n&gt;</register_link> is not <hexnumber>0x00</hexnumber>, the behavior of the Context Identifier Comparator is <arm-defined-word>CONSTRAINED UNPREDICTABLE</arm-defined-word>. In this scenario the comparator might match unexpectedly or might not match.</para>

      </access_permission_text>
      <access_permission_text>
        <para>Writes are <arm-defined-word>CONSTRAINED UNPREDICTABLE</arm-defined-word> if the trace unit is not in the Idle state.</para>
      </access_permission_text>





    

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>