<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
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<?xml-stylesheet href="one_register.xsl" type="text/xsl" ?>







<register_page>
  <registers>
  
    <register is_register="True" is_internal="False" is_stub_entry="False">
      <reg_short_name>TRCCIDCVR&lt;n&gt;</reg_short_name>
        
        <reg_long_name>Trace Context Identifier Comparator Value Registers &lt;n&gt;</reg_long_name>



      
            <reg_condition otherwise="RES0">when FEAT_ETE is implemented, FEAT_TRC_EXT is implemented, and UInt(TRCIDR4.NUMCIDC) > n</reg_condition>
          <reg_array>
              <reg_array_start>0</reg_array_start>
              <reg_array_end>7</reg_array_end>
         </reg_array>
      

    
  <reg_address
      external_access="True"
    mem_map_access="True"
      power_domain="None"
  >
    <reg_component>ETE</reg_component>
    <reg_offset><hexnumber>0x600</hexnumber> + (8 * n)</reg_offset>
    <reg_instance>TRCCIDCVR&lt;n&gt;</reg_instance>
    <reg_access>
      
        
      <reg_access_state>
          <reg_access_level>When OSLockStatus(), or !AllowExternalTraceAccess(addrdesc), or !IsTraceCorePowered()</reg_access_level>
          <reg_access_type>ERROR</reg_access_type>
      </reg_access_state>
        
      <reg_access_state>
          <reg_access_type>RW</reg_access_type>
      </reg_access_state>
    </reg_access>
</reg_address>



          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        



    
      
      <reg_mapping>
        
  

    

  

    <mapped_name filename="AArch64-trccidcvrn.xml">TRCCIDCVR&lt;n&gt;</mapped_name>
  <mapped_type>Architectural</mapped_type>
      <mapped_execution_state>AArch64</mapped_execution_state>
    <mapped_from_startbit>63</mapped_from_startbit>
    <mapped_from_endbit>0</mapped_from_endbit>
    <mapped_to_startbit>63</mapped_to_startbit>
    <mapped_to_endbit>0</mapped_to_endbit>
    <mapped_from_rangeset output="63:0">
      <range>
        <msb>63</msb>
        <lsb>0</lsb>
      </range>
    </mapped_from_rangeset>
    <mapped_to_rangeset output="63:0">
      <range>
        <msb>63</msb>
        <lsb>0</lsb>
      </range>
    </mapped_to_rangeset>

      </reg_mapping>

      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>Contains a Context identifier value.</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
          <reg_group>Trace</reg_group>
      </reg_groups>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>TRCCIDCVR&lt;n&gt; is a 64-bit register.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="64">
  <text_before_fields/>
  <field id="fieldset_0-63_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>VALUE</field_name>
    <field_msb>63</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>63:0</rel_range>
    <field_description order="before">
      <para>Context identifier value. The width of this field is indicated by <register_link state="ext" id="ext-trcidr2.xml">TRCIDR2</register_link>.CIDSIZE. Unimplemented bits are <arm-defined-word>RES0</arm-defined-word>. After a PE Reset, the trace unit assumes that the Context identifier is zero until the PE updates the Context identifier.</para>
    </field_description>
    <field_resets>
      <field_reset reset_type="Trace unit">
        <field_reset_standard_text>AU</field_reset_standard_text>
      </field_reset>
    </field_resets>
  </field>
  <text_after_fields/>
</fields>




<reg_fieldset length="64">
  <fieldat id="fieldset_0-63_0" msb="63" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>
        <reg_variables>
              <reg_variable variable="n" max="7"/>
        </reg_variables>

      <access_mechanisms>
          


  
    
      <access_permission_text>
        <para>Must be programmed if any of the following are true:</para>

      </access_permission_text>
      <access_permission_text>
        <list type="unordered">
<listitem><content><register_link id="ext-trcrsctlrn.xml" state="ext">TRCRSCTLR&lt;a&gt;</register_link>.GROUP == <binarynumber>0b0110</binarynumber> and <register_link id="ext-trcrsctlrn.xml" state="ext">TRCRSCTLR&lt;a&gt;</register_link>.CID[n] == 1.</content>
</listitem><listitem><content><register_link id="ext-trcacatrn.xml" state="ext">TRCACATR&lt;a&gt;</register_link>.CONTEXTTYPE == <binarynumber>0b01</binarynumber> or <binarynumber>0b11</binarynumber> and <register_link id="ext-trcacatrn.xml" state="ext">TRCACATR&lt;a&gt;</register_link>.CONTEXT == n.</content>
</listitem></list>

      </access_permission_text>
      <access_permission_text>
        <para>Writes are <arm-defined-word>CONSTRAINED UNPREDICTABLE</arm-defined-word> if the trace unit is not in the Idle state.</para>
      </access_permission_text>





    

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>