<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
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<?xml-stylesheet href="one_register.xsl" type="text/xsl" ?>







<register_page>
  <registers>
  
    <register is_register="True" is_internal="False" is_stub_entry="False">
      <reg_short_name>TRCCLAIMCLR</reg_short_name>
        
        <reg_long_name>Trace Claim Tag Clear Register</reg_long_name>



      
            <reg_condition otherwise="RES0">when FEAT_ETE is implemented and FEAT_TRC_EXT is implemented</reg_condition>
      

    
  <reg_address
      external_access="True"
    mem_map_access="True"
      power_domain="None"
  >
    <reg_component>ETE</reg_component>
    <reg_offset><hexnumber>0xFA4</hexnumber></reg_offset>
    <reg_instance>TRCCLAIMCLR</reg_instance>
    <reg_access>
      
        
      <reg_access_state>
          <reg_access_level>When OSLockStatus() or !IsTraceCorePowered()</reg_access_level>
          <reg_access_type>ERROR</reg_access_type>
      </reg_access_state>
        
      <reg_access_state>
          <reg_access_type>RW</reg_access_type>
      </reg_access_state>
    </reg_access>
</reg_address>



          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        



    
      
      <reg_mapping>
        
  

    

  

    <mapped_name filename="AArch64-trcclaimclr.xml">TRCCLAIMCLR</mapped_name>
  <mapped_type>Architectural</mapped_type>
      <mapped_execution_state>AArch64</mapped_execution_state>
    <mapped_from_startbit>31</mapped_from_startbit>
    <mapped_from_endbit>0</mapped_from_endbit>
    <mapped_to_startbit>31</mapped_to_startbit>
    <mapped_to_endbit>0</mapped_to_endbit>
    <mapped_from_rangeset output="31:0">
      <range>
        <msb>31</msb>
        <lsb>0</lsb>
      </range>
    </mapped_from_rangeset>
    <mapped_to_rangeset output="31:0">
      <range>
        <msb>31</msb>
        <lsb>0</lsb>
      </range>
    </mapped_to_rangeset>

      </reg_mapping>
      
      <reg_mapping>
        
  

    

  

    <mapped_name filename="AArch64-trcclaimset.xml">TRCCLAIMSET</mapped_name>
  <mapped_type>Architectural</mapped_type>
      <mapped_execution_state>AArch64</mapped_execution_state>
    <mapped_from_startbit>31</mapped_from_startbit>
    <mapped_from_endbit>0</mapped_from_endbit>
    <mapped_to_startbit>31</mapped_to_startbit>
    <mapped_to_endbit>0</mapped_to_endbit>
    <mapped_from_rangeset output="31:0">
      <range>
        <msb>31</msb>
        <lsb>0</lsb>
      </range>
    </mapped_from_rangeset>
    <mapped_to_rangeset output="31:0">
      <range>
        <msb>31</msb>
        <lsb>0</lsb>
      </range>
    </mapped_to_rangeset>

      </reg_mapping>
      
      <reg_mapping>
        
  

    

  

    <mapped_name filename="ext-trcclaimset.xml">TRCCLAIMSET</mapped_name>
  <mapped_type>Architectural</mapped_type>
      <mapped_execution_state>External</mapped_execution_state>
    <mapped_from_startbit>31</mapped_from_startbit>
    <mapped_from_endbit>0</mapped_from_endbit>
    <mapped_to_startbit>31</mapped_to_startbit>
    <mapped_to_endbit>0</mapped_to_endbit>
    <mapped_from_rangeset output="31:0">
      <range>
        <msb>31</msb>
        <lsb>0</lsb>
      </range>
    </mapped_from_rangeset>
    <mapped_to_rangeset output="31:0">
      <range>
        <msb>31</msb>
        <lsb>0</lsb>
      </range>
    </mapped_to_rangeset>

      </reg_mapping>

      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>In conjunction with <register_link state="ext" id="ext-trcclaimset.xml">TRCCLAIMSET</register_link>, provides Claim Tag bits that can be separately set and cleared to indicate whether functionality is in use by a debug agent.</para>

      </purpose_text>
      <purpose_text>
        <para>For additional information, see the CoreSight Architecture Specification.</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
          <reg_group>Trace</reg_group>
      </reg_groups>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>TRCCLAIMCLR is a 32-bit register.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="32">
  <text_before_fields/>
  <field id="fieldset_0-31_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>CLR[&lt;m&gt;]</field_name>
    <field_msb>31</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>31:0</rel_range>
    <field_description order="before">
      <para>Claim Tag Clear. Indicates the current status of Claim Tag bit &lt;m&gt;, and is used to clear Claim Tag bit &lt;m&gt; to 0.</para>
    </field_description>
    <field_description order="after">
      <para>The number of Claim Tag bits implemented is indicated in <register_link state="ext" id="ext-trcclaimset.xml">TRCCLAIMSET</register_link>.</para>
    </field_description>
    <field_array_indexes index_variable="m" element_size="1" range_specifier="m">
      <field_array_index>
        <field_array_start>31</field_array_start>
        <field_array_end>0</field_array_end>
      </field_array_index>
    </field_array_indexes>
    <field_values impdef="False">
      <field_value_instance>
        <field_value>0b0</field_value>
        <field_value_description><para>On a read: Claim Tag bit &lt;m&gt; is not set.</para>
<para>On a write: Ignored.</para></field_value_description>
      </field_value_instance>
      <field_value_instance>
        <field_value>0b1</field_value>
        <field_value_description><para>On a read: Claim Tag bit &lt;m&gt; is set.</para>
<para>On a write: Clear Claim tag bit &lt;m&gt; to 0.</para></field_value_description>
      </field_value_instance>
    </field_values>
    <field_resets>
      <field_reset reset_type="Trace unit">
        <field_reset_number>'0'</field_reset_number>
      </field_reset>
    </field_resets>
    <field_access>
      <field_access_state>
        <field_access_level>When m &gt;= NUM_TRC_CLAIM_TAGS</field_access_level>
        <field_access_type>RAZ/WI</field_access_type>
      </field_access_state>
      <field_access_state>
        <field_access_type>W1C</field_access_type>
      </field_access_state>
    </field_access>
  </field>
  <text_after_fields/>
</fields>




<reg_fieldset length="32">
  <fieldat id="fieldset_0-31_0" label="CLR[31]" msb="31" lsb="31"/>
  <fieldat id="fieldset_0-31_0" label="CLR[30]" msb="30" lsb="30"/>
  <fieldat id="fieldset_0-31_0" label="CLR[29]" msb="29" lsb="29"/>
  <fieldat id="fieldset_0-31_0" label="CLR[28]" msb="28" lsb="28"/>
  <fieldat id="fieldset_0-31_0" label="CLR[27]" msb="27" lsb="27"/>
  <fieldat id="fieldset_0-31_0" label="CLR[26]" msb="26" lsb="26"/>
  <fieldat id="fieldset_0-31_0" label="CLR[25]" msb="25" lsb="25"/>
  <fieldat id="fieldset_0-31_0" label="CLR[24]" msb="24" lsb="24"/>
  <fieldat id="fieldset_0-31_0" label="CLR[23]" msb="23" lsb="23"/>
  <fieldat id="fieldset_0-31_0" label="CLR[22]" msb="22" lsb="22"/>
  <fieldat id="fieldset_0-31_0" label="CLR[21]" msb="21" lsb="21"/>
  <fieldat id="fieldset_0-31_0" label="CLR[20]" msb="20" lsb="20"/>
  <fieldat id="fieldset_0-31_0" label="CLR[19]" msb="19" lsb="19"/>
  <fieldat id="fieldset_0-31_0" label="CLR[18]" msb="18" lsb="18"/>
  <fieldat id="fieldset_0-31_0" label="CLR[17]" msb="17" lsb="17"/>
  <fieldat id="fieldset_0-31_0" label="CLR[16]" msb="16" lsb="16"/>
  <fieldat id="fieldset_0-31_0" label="CLR[15]" msb="15" lsb="15"/>
  <fieldat id="fieldset_0-31_0" label="CLR[14]" msb="14" lsb="14"/>
  <fieldat id="fieldset_0-31_0" label="CLR[13]" msb="13" lsb="13"/>
  <fieldat id="fieldset_0-31_0" label="CLR[12]" msb="12" lsb="12"/>
  <fieldat id="fieldset_0-31_0" label="CLR[11]" msb="11" lsb="11"/>
  <fieldat id="fieldset_0-31_0" label="CLR[10]" msb="10" lsb="10"/>
  <fieldat id="fieldset_0-31_0" label="CLR[9]" msb="9" lsb="9"/>
  <fieldat id="fieldset_0-31_0" label="CLR[8]" msb="8" lsb="8"/>
  <fieldat id="fieldset_0-31_0" label="CLR[7]" msb="7" lsb="7"/>
  <fieldat id="fieldset_0-31_0" label="CLR[6]" msb="6" lsb="6"/>
  <fieldat id="fieldset_0-31_0" label="CLR[5]" msb="5" lsb="5"/>
  <fieldat id="fieldset_0-31_0" label="CLR[4]" msb="4" lsb="4"/>
  <fieldat id="fieldset_0-31_0" label="CLR[3]" msb="3" lsb="3"/>
  <fieldat id="fieldset_0-31_0" label="CLR[2]" msb="2" lsb="2"/>
  <fieldat id="fieldset_0-31_0" label="CLR[1]" msb="1" lsb="1"/>
  <fieldat id="fieldset_0-31_0" label="CLR[0]" msb="0" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>

      <access_mechanisms>
          






    

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>