<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
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<?xml-stylesheet href="one_register.xsl" type="text/xsl" ?>







<register_page>
  <registers>
  
    <register is_register="True" is_internal="False" is_stub_entry="False">
      <reg_short_name>TRCIDR1</reg_short_name>
        
        <reg_long_name>Trace ID Register 1</reg_long_name>



      
            <reg_condition otherwise="RES0">when FEAT_ETE is implemented and FEAT_TRC_EXT is implemented</reg_condition>
      

    
  <reg_address
      external_access="True"
    mem_map_access="True"
      power_domain="None"
  >
    <reg_component>ETE</reg_component>
    <reg_offset><hexnumber>0x1E4</hexnumber></reg_offset>
    <reg_instance>TRCIDR1</reg_instance>
    <reg_access>
      
        
      <reg_access_state>
          <reg_access_level>When OSLockStatus() or !IsTraceCorePowered()</reg_access_level>
          <reg_access_type>ERROR</reg_access_type>
      </reg_access_state>
        
      <reg_access_state>
          <reg_access_type>RO</reg_access_type>
      </reg_access_state>
    </reg_access>
</reg_address>



          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        



    
      
      <reg_mapping>
        
  

    

  

    <mapped_name filename="AArch64-trcidr1.xml">TRCIDR1</mapped_name>
  <mapped_type>Architectural</mapped_type>
      <mapped_execution_state>AArch64</mapped_execution_state>
    <mapped_from_startbit>31</mapped_from_startbit>
    <mapped_from_endbit>0</mapped_from_endbit>
    <mapped_to_startbit>31</mapped_to_startbit>
    <mapped_to_endbit>0</mapped_to_endbit>
    <mapped_from_rangeset output="31:0">
      <range>
        <msb>31</msb>
        <lsb>0</lsb>
      </range>
    </mapped_from_rangeset>
    <mapped_to_rangeset output="31:0">
      <range>
        <msb>31</msb>
        <lsb>0</lsb>
      </range>
    </mapped_to_rangeset>

      </reg_mapping>

      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>Returns the tracing capabilities of the trace unit.</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
          <reg_group>Trace</reg_group>
      </reg_groups>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>TRCIDR1 is a 32-bit register.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="32">
  <text_before_fields/>
  <field id="fieldset_0-31_24" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="True" is_partial_field="False" is_conditional_field_name="False">
    <field_name>DESIGNER</field_name>
    <field_msb>31</field_msb>
    <field_lsb>24</field_lsb>
    <rel_range>31:24</rel_range>
    <field_description order="before">
      <para>Indicates which company designed the trace unit. The permitted values of this field are the same as <register_link state="AArch64" id="AArch64-midr_el1.xml">MIDR_EL1</register_link>.Implementer.</para>
    </field_description>
    <field_description order="after">
      <para>This field has an <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> value.</para>
    </field_description>
    <field_access>
      <field_access_state>
        <field_access_type>RO</field_access_type>
      </field_access_state>
    </field_access>
  </field>
  <field id="fieldset_0-23_16" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES0">
    <field_msb>23</field_msb>
    <field_lsb>16</field_lsb>
    <rel_range>23:16</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES0</arm-defined-word>.</para>
    </field_description>
  </field>
  <field id="fieldset_0-15_12" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False" rwtype="RES1">
    <field_msb>15</field_msb>
    <field_lsb>12</field_lsb>
    <rel_range>15:12</rel_range>
    <field_description order="before"/>
    <field_description order="before">
      <para>Reserved, <arm-defined-word>RES1</arm-defined-word>.</para>
    </field_description>
  </field>
  <field id="fieldset_0-11_8" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="True" is_partial_field="False" is_conditional_field_name="False">
    <field_name>TRCARCHMAJ</field_name>
    <field_msb>11</field_msb>
    <field_lsb>8</field_lsb>
    <rel_range>11:8</rel_range>
    <field_description order="before">
      <para>Major architecture version.</para>
    </field_description>
    <field_description order="after"><para>All other values are reserved.</para>
<para>This field reads as <binarynumber>0b1111</binarynumber>.</para></field_description>
    <field_values impdef="False">
      <field_value_instance>
        <field_value>0b1111</field_value>
        <field_value_description>
          <para>If both TRCIDR1.TRCARCHMAJ and TRCIDR1.TRCARCHMIN == <hexnumber>0xF</hexnumber> then refer to <register_link state="ext" id="ext-trcdevarch.xml">TRCDEVARCH</register_link>.</para>
        </field_value_description>
      </field_value_instance>
    </field_values>
    <field_access>
      <field_access_state>
        <field_access_type>RO</field_access_type>
      </field_access_state>
    </field_access>
  </field>
  <field id="fieldset_0-7_4" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="True" is_partial_field="False" is_conditional_field_name="False">
    <field_name>TRCARCHMIN</field_name>
    <field_msb>7</field_msb>
    <field_lsb>4</field_lsb>
    <rel_range>7:4</rel_range>
    <field_description order="before">
      <para>Minor architecture version.</para>
    </field_description>
    <field_description order="after"><para>All other values are reserved.</para>
<para>This field reads as <binarynumber>0b1111</binarynumber>.</para></field_description>
    <field_values impdef="False">
      <field_value_instance>
        <field_value>0b1111</field_value>
        <field_value_description>
          <para>If both TRCIDR1.TRCARCHMAJ and TRCIDR1.TRCARCHMIN == <hexnumber>0xF</hexnumber> then refer to <register_link state="ext" id="ext-trcdevarch.xml">TRCDEVARCH</register_link>.</para>
        </field_value_description>
      </field_value_instance>
    </field_values>
    <field_access>
      <field_access_state>
        <field_access_type>RO</field_access_type>
      </field_access_state>
    </field_access>
  </field>
  <field id="fieldset_0-3_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="True" is_partial_field="False" is_conditional_field_name="False">
    <field_name>REVISION</field_name>
    <field_msb>3</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>3:0</rel_range>
    <field_description order="before"><para>Implementation revision.</para>
<para>Returns an <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> value that identifies the revision of the trace unit.</para>
<para>Arm deprecates any use of this field and recommends that implementations set this field to zero.</para></field_description>
    <field_description order="after">
      <para>This field has an <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> value.</para>
    </field_description>
    <field_access>
      <field_access_state>
        <field_access_type>RO</field_access_type>
      </field_access_state>
    </field_access>
  </field>
  <text_after_fields/>
</fields>




<reg_fieldset length="32">
  <fieldat id="fieldset_0-31_24" msb="31" lsb="24"/>
  <fieldat id="fieldset_0-23_16" msb="23" lsb="16"/>
  <fieldat id="fieldset_0-15_12" msb="15" lsb="12"/>
  <fieldat id="fieldset_0-11_8" msb="11" lsb="8"/>
  <fieldat id="fieldset_0-7_4" msb="7" lsb="4"/>
  <fieldat id="fieldset_0-3_0" msb="3" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>

      <access_mechanisms>
          






    

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>