TRCIDR5 Trace ID Register 5 when FEAT_ETE is implemented and FEAT_TRC_EXT is implemented ETE 0x1F4 TRCIDR5 When OSLockStatus() or !IsTraceCorePowered() ERROR RO TRCIDR5 Architectural AArch64 31 0 31 0 31 0 31 0 Returns the tracing capabilities of the trace unit. Trace TRCIDR5 is a 32-bit register. OE 31 31 31 Indicates support for the ETE Trace Output Enable. When FEAT_ETEv1p3 is implemented and when any IMPLEMENTATION DEFINED trace output interface is implemented, this field is 1. 0b0 ETE Trace Output Enable is not implemented. 0b1 ETE Trace Output Enable is implemented. RO NUMCNTR 30 28 30:28 Indicates the number of Counters that are available for tracing. All other values are reserved. If TRCIDR4.NUMRSPAIR == 0b0000 then this field is 0b000. 0b000..0b100 The number of Counters implemented. RO NUMSEQSTATE 27 25 27:25 Indicates if the Sequencer is implemented and the number of Sequencer states that are implemented. All other values are reserved. If TRCIDR4.NUMRSPAIR == 0b0000 then this field is 0b000. 0b000 The Sequencer is not implemented. 0b100 Four Sequencer states are implemented. RO 24 24 24 Reserved, RES0. LPOVERRIDE 23 23 23 Indicates support for Low-power Override Mode. 0b0 The trace unit does not support Low-power Override Mode. 0b1 The trace unit supports Low-power Override Mode. RO ATBTRIG 22 22 22 Indicates if the implementation can support ATB triggers. If TRCIDR4.NUMRSPAIR == 0b0000 then this field is 0. 0b0 The implementation does not support ATB triggers. 0b1 The implementation supports ATB triggers. RO TRACEIDSIZE 21 16 21:16 Indicates the trace ID width. All other values are reserved. AMBA ATB requires a 7-bit trace ID width. 0b000000 The external trace interface is not implemented. 0b000111 The implementation supports a 7-bit trace ID. RO 15 12 15:12 Reserved, RES0. NUMEXTINSEL 11 9 11:9 Indicates how many External Input Selector resources are implemented. All other values are reserved. 0b000..0b100 The number of External Input Selector resources implemented. RO NUMEXTIN 8 0 8:0 Indicates how many External Inputs are implemented. All other values are reserved. 0b111111111 Unified PMU event selection. RO 2026-03-26 20:27:25 2026-03_rel