<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
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<?xml-stylesheet href="one_register.xsl" type="text/xsl" ?>







<register_page>
  <registers>
  
    <register is_register="True" is_internal="False" is_stub_entry="False">
      <reg_short_name>TRCIDR8</reg_short_name>
        
        <reg_long_name>Trace ID Register 8</reg_long_name>



      
            <reg_condition otherwise="RES0">when FEAT_ETE is implemented and FEAT_TRC_EXT is implemented</reg_condition>
      

    
  <reg_address
      external_access="True"
    mem_map_access="True"
      power_domain="None"
  >
    <reg_component>ETE</reg_component>
    <reg_offset><hexnumber>0x180</hexnumber></reg_offset>
    <reg_instance>TRCIDR8</reg_instance>
    <reg_access>
      
        
      <reg_access_state>
          <reg_access_level>When OSLockStatus() or !IsTraceCorePowered()</reg_access_level>
          <reg_access_type>ERROR</reg_access_type>
      </reg_access_state>
        
      <reg_access_state>
          <reg_access_type>RO</reg_access_type>
      </reg_access_state>
    </reg_access>
</reg_address>



          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        



    
      
      <reg_mapping>
        
  

    

  

    <mapped_name filename="AArch64-trcidr8.xml">TRCIDR8</mapped_name>
  <mapped_type>Architectural</mapped_type>
      <mapped_execution_state>AArch64</mapped_execution_state>
    <mapped_from_startbit>31</mapped_from_startbit>
    <mapped_from_endbit>0</mapped_from_endbit>
    <mapped_to_startbit>31</mapped_to_startbit>
    <mapped_to_endbit>0</mapped_to_endbit>
    <mapped_from_rangeset output="31:0">
      <range>
        <msb>31</msb>
        <lsb>0</lsb>
      </range>
    </mapped_from_rangeset>
    <mapped_to_rangeset output="31:0">
      <range>
        <msb>31</msb>
        <lsb>0</lsb>
      </range>
    </mapped_to_rangeset>

      </reg_mapping>

      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>Returns the maximum speculation depth of the instruction trace element stream.</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
          <reg_group>Trace</reg_group>
      </reg_groups>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>TRCIDR8 is a 32-bit register.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="32">
  <text_before_fields/>
  <field id="fieldset_0-31_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="True" is_partial_field="False" is_conditional_field_name="False">
    <field_name>MAXSPEC</field_name>
    <field_msb>31</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>31:0</rel_range>
    <field_description order="before">
      <para>Indicates the maximum speculation depth of the instruction trace element stream. This is the maximum number of P0 elements in the trace element stream that can be speculative at any time.</para>
    </field_description>
    <field_description order="after">
      <para>This field has an <arm-defined-word>IMPLEMENTATION DEFINED</arm-defined-word> value.</para>
    </field_description>
    <field_access>
      <field_access_state>
        <field_access_type>RO</field_access_type>
      </field_access_state>
    </field_access>
  </field>
  <text_after_fields/>
</fields>




<reg_fieldset length="32">
  <fieldat id="fieldset_0-31_0" msb="31" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>

      <access_mechanisms>
          






    

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>