TRCLSR Trace Lock Status Register when FEAT_ETE is implemented and FEAT_TRC_EXT is implemented ETE 0xFB4 TRCLSR When !IsTraceCorePowered() ERROR RO Indicates whether the Software Lock is implemented, and the current status of the Software Lock. For additional information, see the CoreSight Architecture Specification. Trace Management TRCLSR is a 32-bit register. 31 3 31:3 Reserved, RES0. nTT 2 2 2 Software lock size. Reads as 0b0. RO SLK 1 1 1 The current Software Lock status. This field reads as 0. 0b0 Software Lock is unlocked. 0b1 Software Lock is locked. Writes to the other registers in this component, except for the TRCLAR, are ignored. SLI 0 0 0 Indicates whether the Software Lock is implemented. This field reads as 0. 0b0 Software Lock is not implemented. Writes to the TRCLAR are ignored. 0b1 Software Lock is implemented. RO External debugger accesses to this register are unaffected by the OS Lock. 2026-03-26 20:27:25 2026-03_rel