TRCPDSR Trace PowerDown Status Register when FEAT_ETE is implemented and FEAT_TRC_EXT is implemented ETE 0x314 TRCPDSR When !IsTraceCorePowered() ERROR RO Indicates the power status of the trace unit. Trace Management TRCPDSR is a 32-bit register. 31 6 31:6 Reserved, RES0. OSLK 5 5 5 OS Lock Status. This field indicates the state of the PE OS Lock. 0b0 The OS Lock is unlocked. 0b1 The OS Lock is locked. 4 2 4:2 Reserved, RES0. STICKYPD 1 1 1 Sticky powerdown status. Indicates whether the trace register state is valid. This field is set to 1 if the power to the trace unit core power domain is removed and the trace unit register state is not valid. The STICKYPD field is read-sensitive. On a read of the TRCPDSR, this field is cleared to 0 after the register has been read. 0b0 The state of TRCOSLSR and the trace registers are valid. 0b1 The state of TRCOSLSR and the trace registers might not be valid. AU RC/WI POWER 0 0 0 Power Status. 0b0 The trace unit core power domain is not powered. All trace unit registers are not accessible and they all return an error response. 0b1 The trace unit core power domain is powered. Trace unit registers are accessible. RAO/WI External debugger accesses to this register are unaffected by the OS Lock. 2026-03-26 20:27:25 2026-03_rel