TRCQCTLR Trace Q Element Control Register when FEAT_ETE is implemented, FEAT_TRC_EXT is implemented, and TRCIDR0.QFILT == '1' ETE 0x044 TRCQCTLR When OSLockStatus(), or !AllowExternalTraceAccess(addrdesc), or !IsTraceCorePowered() ERROR RW TRCQCTLR Architectural AArch64 31 0 31 0 31 0 31 0 Controls when Q elements are enabled. Trace TRCQCTLR is a 32-bit register. 31 9 31:9 Reserved, RES0. MODE 8 8 8 Selects whether the Address Range Comparators selected by TRCQCTLR.RANGE indicate address ranges where the trace unit is permitted to generate Q elements or address ranges where the trace unit is not permitted to generate Q elements: 0b0 Exclude mode. The Address Range Comparators selected by TRCQCTLR.RANGE indicate address ranges where the trace unit must not generate Q elements. If no ranges are selected, Q elements are permitted across the entire memory map. 0b1 Include Mode. The Address Range Comparators selected by TRCQCTLR.RANGE indicate address ranges where the trace unit can generate Q elements. If all the implemented bits in RANGE are set to 0 then Q elements are disabled. AU RANGE[<m>] 7 0 7:0 Specifies whether Address Range Comparator <m> controls Q elements. 7 0 0b0 The address range that Address Range Comparator <m> defines is not selected. 0b1 The address range that Address Range Comparator <m> defines is selected. AU When m >= UInt(TRCIDR4.NUMACPAIRS) RES0 RW Must be programmed if TRCCONFIGR.QE != 0b00. Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state. 2026-03-26 20:27:25 2026-03_rel