TRCSSCCR<n> Trace Single-shot Comparator Control Register <n> when FEAT_ETE is implemented, FEAT_TRC_EXT is implemented, and UInt(TRCIDR4.NUMSSCC) > n 0 7 ETE 0x280 + (4 * n) TRCSSCCR<n> When OSLockStatus(), or !AllowExternalTraceAccess(addrdesc), or !IsTraceCorePowered() ERROR RW TRCSSCCR<n> Architectural AArch64 31 0 31 0 31 0 31 0 Controls the corresponding Single-shot Comparator Control resource. Trace TRCSSCCR<n> is a 32-bit register. 31 25 31:25 Reserved, RES0. RST 24 24 24 Selects the Single-shot Comparator Control mode. 0b0 The Single-shot Comparator Control is in single-shot mode. 0b1 The Single-shot Comparator Control is in multi-shot mode. AU ARC[<m>] 23 16 23:16 Selects one or more Address Range Comparators for Single-shot control. 7 0 0b0 The Address Range Comparator <m>, is not selected for Single-shot control. 0b1 The Address Range Comparator <m>, is selected for Single-shot control. AU When m >= UInt(TRCIDR4.NUMACPAIRS) RES0 RW SAC[<m>] 15 0 15:0 Selects one or more Single Address Comparators for Single-shot control. 15 0 0b0 The Single Address Comparator <m>, is not selected for Single-shot control. 0b1 The Single Address Comparator <m>, is selected for Single-shot control. AU When m >= UInt(TRCIDR4.NUMACPAIRS) * 2 RES0 RW Must be programmed if any TRCRSCTLR<a>.GROUP == 0b0011 and TRCRSCTLR<a>.SINGLE_SHOT[n] == 1. Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state. 2026-03-26 20:27:25 2026-03_rel