TRCSTALLCTLR Trace Stall Control Register when FEAT_ETE is implemented, FEAT_TRC_EXT is implemented, and TRCIDR3.STALLCTL == '1' ETE 0x02C TRCSTALLCTLR When OSLockStatus(), or !AllowExternalTraceAccess(addrdesc), or !IsTraceCorePowered() ERROR RW TRCSTALLCTLR Architectural AArch64 31 0 31 0 31 0 31 0 Enables trace unit functionality that prevents trace unit buffer overflows. Trace TRCSTALLCTLR is a 32-bit register. 31 14 31:14 Reserved, RES0. NOOVERFLOW 13 13 0 Trace overflow prevention. Enabling this feature might cause a significant performance impact. 0b0 Trace unit buffer overflow prevention is disabled. 0b1 Trace unit buffer overflow prevention is enabled. AU When TRCIDR3.NOOVERFLOW == '1' 13 13 13 Reserved, RES0. Otherwise 12 9 12:9 Reserved, RES0. ISTALL 8 8 8 Instruction stall control. Controls if a trace unit can stall the PE when the trace buffer space is less than LEVEL. 0b0 The trace unit must not stall the PE. 0b1 The trace unit can stall the PE. AU 7 4 7:4 Reserved, RES0. LEVEL 3 0 3:0 Threshold level field. The field can support 16 monotonic levels from 0b0000 to 0b1111. The value 0b0000 defines the Minimal invasion level. This setting has a greater risk of a trace unit buffer overflow. The value 0b1111 defines the Maximum invasion level. This setting has a reduced risk of a trace unit buffer overflow. For some implementations, invasion might occur at the minimal invasion level. One or more of the least significant bits of LEVEL are permitted to be RES0. Arm recommends that LEVEL[3:2] are fully implemented. Arm strongly recommends that LEVEL[3] is always implemented. If one or more bits are RES0 and are written with a nonzero value, the effective value of LEVEL is rounded down to the nearest power of 2 value which has the RES0 bits as zero. For example, if LEVEL[1:0] are RES0 and a value of 0b1110 is written to LEVEL, the effective value of LEVEL is 0b1100. AU Must be programmed if implemented. Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state. 2026-03-26 20:27:25 2026-03_rel