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AArch32 Registers
AArch64 Registers
AArch32 Instructions
AArch64 Instructions
Index by Encoding
External Registers
External Registers by Offset
Registers by Functional Group
Proprietary Notice

,

Copyright © 2010-2026 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.

 register block instruction

, , = 0 - , , n = -

This describes , and and .

The characteristics are:

Traps and Enables

For a description of the prioritization of any generated exceptions, see section G1.11.2 (Exception priority order) in the Arm® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile for exceptions taken to AArch32 state, and section D1.13.2 (Synchronous exception prioritization) for exceptions taken to AArch64 state. Subject to the prioritization rules:

For a description of the prioritization of any generated exceptions, see section D1.13.2 (Synchronous exception prioritization) in the Arm® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile. Subject to the prioritization rules:

There are no traps or enables affecting this instruction.

There are no traps or enables affecting this register.

Configuration

This is present only from Arm . Otherwise, direct accesses to are .

There are no configuration notes.

There are no configuration notes.

Attributes

This block register is part of the block.

Field descriptions

See .

Executing

Accessing

Contents

Offset Name Accessor condition Register condition Most permissive access
- -

Direct accesses to other offsets in this block are .

Accessing this register depends on which field is being accessed; see the register field descriptions for the states that they are accessible in.

The meanings of the conditions in the table above are summarised in 'Access permissions for the External debug interface registers' in the Arm® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile, section H8.6.1. The priority at which each condition applies is from highest priority on the left to lowest on the right.
Component Frame Offset Instance Range
:

, accesses to this .

Accessible as follows:
  • , Otherwise, The accesses to this .

Accesses to this .

 generate an error response are [:]

can be accessed through a memory-mapped access to the external debug interface:

can be accessed through the external debug interface:

can be accessed through the memory-mapped interfaces:

Purpose


    

bit s [] () External register System instruction register [] [ ] : ] () External register System instruction register

are architecturally mapped to is architecturally mapped to can be mapped to performs the same function as , but this is not architecturally mandated .

 bit s [] () bit s [] ()

The register instance are is architecturally mapped to register instance .

When , and the AArch64 AArch32 external register [] , are mapped to each other.

.

For all register layouts:

 register instruction <Xt> <Rt>

This has no applicable fields.

The value in the register specified by is ignored.

 The following pseudocode shows the operation of this register.

To execute the instruction when :

The instruction is executed as:

To access the when :

The instruction is encoded in the System instruction encoding space as follows:

Register access is encoded as follows:

Otherwise

variant :

:

variant
: Bits[] # Additional information for the encoding for Additional information for this encoding Additional information
# . , bit [ , bits [ Bit [ Bits [ : , : ] Bits[]
From Arm: :
Otherwise:

[n], for n = to [] [] [ [:] of bits
, for = to , , where each field is bit wide bits wide

The reset behavior of this field is:

    On an On a
  • reset:
  • reset,
or the On a reset, the value of this field is unchanged. or the On a reset, the value of this field is unchanged. It is IMPLEMENTATION DEFINED when On a n reset, when When , in In the instance, when When implemented in the domain, in In a system where the PE resets into ,
  • this field resets to an IMPLEMENTATION DEFINED choice between:
    • this field resets to an IMPLEMENTATION DEFINED choice between:
  • this field resets to
    • this field resets to     . The value in the value in -.xml . . An architecturally an architecturally UNKNOWN value. An an UNKNOWN value. An an IMPLEMENTATION DEFINED value. A value determined by an input configuration signal. a value determined by an input configuration signal. the expression .

    The value of this field is an IMPLEMENTATION DEFINED choice of:
    Name Meaning Applies when
    # encoding for

    The table above shows all possible values of this field. The values this field can take in the current implementation are: is the value of this field in the current implementation.

    • .
    • On read:

    • On write:

    Accessing this field has the following behaviour, dependent upon the active instance:

    In the instance, accessing this field has the following behavior:

    • , access to this field . . Otherwise, Otherwise, access is: access to this field .
    access to this field

    Accessing this field has the following behavior:

    Accessing this field has the following behavior:

    • , access to this field . Otherwise: Otherwise, Otherwise, access is: access to this field .

    , access Access to this field .

    When and or , access to this field is as follows: : Access access to this field if all any the following are true:
    • .
      •
    : , access to this field .
    • . Otherwise: Otherwise, Otherwise: access to this field . .
    returns an Error is

    encoding : Bits[] encoding for

    • , .
      •

    Executing

    Accessing

    instruction register

    can be accessed through the memory-mapped interfaces:

    can be accessed through the external debug interface:

    Accesses to this use the following encodings in the System encoding space:

    Accesses to this use the following encodings:

    Accesses to this use the following encodings:

    ; Where =

    pseudocode

    <> , <> 'True' <:0> <:> :

    This syntax uses the following encoding in the System instruction encoding space:
      0
  • <> is in the range - .
    •
  • <> has no valid values.
    •
  • <> can take the values: .
    •      0 Error: slice (<:>) is taken within a range that is below the variable's minimum value ()! Error: slice (<:>) is taken within a range that is above the variable's maximum value ()! Error: slice (<:>) is taken within a range that is below the variable's minimum value ()! Error: slice (<:>) is taken within a range that is above the variable's maximum value ()! 0

    This instruction is executed using with the following syntax:

     read written modified

    This register can be using with the following syntax:

    , <>

    Accessibility

    The instruction is executable as follows:

    Accessible as follows:
    <> Configuration Accessibility Instance
    EL0 EL1 EL2 EL3
    -

    When : When : When : In both Security states, and not dependent on other configuration bits: Not dependent on other configuration bits:

    EL is not implemented is implemented is implemented and is using EL is highest implemented Exception level == SCR HCR SCR_EL3 HCR_EL2 and && . . ( . || . )

    Note