PMAUTHSTATUS Performance Monitors Authentication Status register PMU when FEAT_PMUv3_EXT is implemented and FEAT_PMUv3 is implemented PMU 0xFB8 When FEAT_DoPD is implemented and !IsCorePowered() ERROR RO Provides information about the state of the IMPLEMENTATION DEFINED authentication interface for Performance Monitors. PMU If FEAT_DoPD is implemented, this register is in the Core power domain. If FEAT_DoPD is not implemented, this register is in the Debug power domain. This register is OPTIONAL, and is required for CoreSight compliance. Arm recommends that this register is implemented. PMAUTHSTATUS is a 32-bit register. 31 28 31:28 Reserved, RES0. RTNID 27 26 27:26 Root non-invasive debug. This field has the same value as DBGAUTHSTATUS_EL1.RTNID. RTID 25 24 25:24 Root invasive debug. 0b00 Not implemented. 23 16 23:16 Reserved, RES0. RLNID 15 14 15:14 Realm non-invasive debug. This field has the same value as DBGAUTHSTATUS_EL1.RLNID. RLID 13 12 13:12 Realm invasive debug. 0b00 Not implemented. 11 8 11:8 Reserved, RES0. SNID 7 6 7:6 Holds the same value as DBGAUTHSTATUS_EL1.SNID. SID 5 4 5:4 Secure invasive debug. All other values are reserved. 0b00 Not implemented. RO NSNID 3 2 3:2 Holds the same value as DBGAUTHSTATUS_EL1.NSNID. NSID 1 0 1:0 Non-secure invasive debug. All other values are reserved. 0b00 Not implemented. RO Accessible at offset 0xFB8 from PMU 2026-03-26 20:27:25 2026-03_rel