PMCCNTR_EL0 Performance Monitors Cycle Counter PMU when FEAT_PMUv3_EXT is implemented and FEAT_PMUv3 is implemented PMU 0x0F8 When DoubleLockStatus(), or !IsCorePowered(), or !AllowExternalPMUAccess(addrdesc) ERROR When (FEAT_PMUv3_EXTPMN is not implemented, or !IsMostSecureAccess(addrdesc), or PMCCR().OSLO == '0') and OSLockStatus() ERROR RW PMU 0x0F8 When DoubleLockStatus(), or !IsCorePowered(), or !AllowExternalPMUAccess(addrdesc) ERROR When (FEAT_PMUv3_EXTPMN is not implemented, or !IsMostSecureAccess(addrdesc), or PMCCR().OSLO == '0') and OSLockStatus() ERROR When SoftwareLockStatus(addrdesc) RO RW PMU 0x0FC When DoubleLockStatus(), or !IsCorePowered(), or !AllowExternalPMUAccess(addrdesc) ERROR When (FEAT_PMUv3_EXTPMN is not implemented, or !IsMostSecureAccess(addrdesc), or PMCCR().OSLO == '0') and OSLockStatus() ERROR When SoftwareLockStatus(addrdesc) RO RW PMCCNTR_EL0 Architectural AArch64 63 0 63 0 63 0 63 0 PMCCNTR Architectural AArch32 63 0 63 0 63 0 63 0 Holds the value of the processor Cycle Counter, CCNT, that counts processor clock cycles. For more information, see 'Time as measured by the Performance Monitors cycle counter'. PMCCFILTR_EL0 determines the modes and states in which the PMCCNTR_EL0 can increment. PMU PMCCNTR_EL0 is in the Core power domain. PMCCNTR_EL0 is a 64-bit register. CCNT 63 0 63:0 Cycle count. Depending on the values of PMCR_EL0.{LC,D}, the cycle count increments in one of the following ways: Every processor clock cycle. Every 64th processor clock cycle. Writing 1 to PMCR_EL0.C sets this field to 0. AU AU [63:0] Accessible at offset 0x0F8 from PMU When FEAT_PMUv3_EXT64 is implemented [31:0] Accessible at offset 0x0F8 from PMU When FEAT_PMUv3_EXT32 is implemented [63:32] Accessible at offset 0x0FC from PMU When FEAT_PMUv3_EXT32 is implemented 2026-03-26 20:27:25 2026-03_rel