PMCCR PMU Configuration Control Register PMU when FEAT_PMUv3_EXTPMN is implemented PMU 0xE58 When DoubleLockStatus() or !IsCorePowered() ERROR When !IsMostSecureAccess(addrdesc) RAZ/WI RW Contains PMU configuration controls. PMU PMCCR is a 64-bit register. 63 9 63:9 Reserved, RES0. OSLO 8 8 0 OS Lock Override. 0b0 No external access to any Performance Monitor register is affected by this control. 0b1 For the purpose of determining the access permissions of Performance Monitor registers, an external access that is a Most secure access ignores OSLSR_EL1.OSLK. '0' When FEAT_PMUv3_EXTPMN is implemented 8 8 8 Reserved, RES0. Otherwise EPME 7 7 0 External Enable. The counters affected by this field are the event counters in the third range. Other event counters, PMCCNTR_EL0, and, if FEAT_PMUv3_ICNTR is implemented, PMICNTR_EL0 are not affected by this field. If the Effective value of PMCCR.EPMN is equal to NUM_PMU_COUNTERS, then this field has no effect. 0b0 Affected counters are disabled and do not count. 0b1 Affected counters are enabled by PMCNTENSET_EL0. '0' When FEAT_PMUv3_EXTPMN is implemented 7 7 7 Reserved, RES0. Otherwise 6 5 6:5 Reserved, RES0. EPMN 4 0 4:0 Defines the number of event counters PMEVCNTR<n>_EL0 and, if FEAT_PMUv3_SS is implemented, snapshot registers PMEVCNTSVR<n>_EL1, that are reserved for external use. PMCCR.EPMN divides the event counters into event counters that are accessible from self-hosted software, and which might be further divided into first and second ranges by MDCR_EL2.HPMN, and a third range that is inaccessible from self-hosted software. If PMCCR.EPMN is not 0 and is less than the number of PMU event counters implemented by the PE, NUM_PMU_COUNTERS, then event counters [0..(PMCCR.EPMN-1)] are in the first and second ranges, and event counters [PMCCR.EPMN..(NUM_PMU_COUNTERS-1)] are in the third range. If PMCCR.EPMN is equal to NUM_PMU_COUNTERS, or FEAT_PMUv3_EXTPMN is not implemented, then all of the following apply: All counters are in the first and second ranges. No counters are in the third range. If PMCCR.EPMN is zero, then all of the following apply: No counters are in the first and second ranges. All counters are in the third range. All the following apply for an event counter PMEVCNTR<n>_EL0 in the third range: The counter is accessible to a Most secure access of PMEVCNTR<n>_EL0. That is, an external access which is one of the following: Root access, when FEAT_RME is implemented. Secure access, when FEAT_RME is not implemented and Secure state is implemented. Non-secure access, otherwise. The counter is not accessible to other external accesses, or as the System register PMEVCNTR<n>_EL0 at any Exception level. The counter overflow flag PMOVSSET_EL0[n] is set on unsigned overflow of PMEVCNTR<n>_EL0[63:0]. PMCCR.EPME and PMCNTENSET_EL0 enable operation of the event counter. If FEAT_PMUv3_SS is implemented, then all of the following apply for an event counter snapshot register PMEVCNTSVR<n>_EL1 in the third range: The event counter snapshot register is accessible to a Most secure access of PMEVCNTSVR<n>_EL1. The event counter snapshot register is not accessible to other external accesses, or as the System register PMEVCNTSVR<n>_EL1 at any Exception level. For information about counters in the first and second ranges, see the description of MDCR_EL2.HPMN. Values greater than NUM_PMU_COUNTERS are reserved. If this field is set to a reserved value, then the following CONSTRAINED UNPREDICTABLE behaviors apply: The value returned by an external read of PMCCR.EPMN is UNKNOWN and less than or equal to 31. For the purpose of indirect reads of PMCCR.EPMN as a result of the following reads, the Effective value of PMCCR.EPMN is UNKNOWN and less than or equal to 31: Direct reads of PMCR_EL0.N or PMCR.N. Direct reads of MDCR_EL2.HPMN. External reads of PMCFGR.N. If FEAT_PMUv3_ICNTR is implemented, external reads of PMCGCR0.CG0NC. For all other purposes the Effective value of PMCCR.EPMN is UNKNOWN and less than or equal to NUM_PMU_COUNTERS. If FEAT_PMUv3_EXTPMN is not implemented, then the Effective value of PMCCR.EPMN is NUM_PMU_COUNTERS. NUM_PMU_COUNTERS When FEAT_PMUv3_EXTPMN is implemented 4 0 4:0 Reserved, RES0. Otherwise Accessible at offset 0xE58 from PMU 2026-03-26 20:27:25 2026-03_rel