PMCEID0 Performance Monitors Common Event Identification register 0 PMU when FEAT_PMUv3_EXT32 is implemented and FEAT_PMUv3 is implemented PMU 0xE20 When DoubleLockStatus(), or !IsCorePowered(), or !AllowExternalPMUAccess(addrdesc) ERROR When (FEAT_PMUv3_EXTPMN is not implemented, or !IsMostSecureAccess(addrdesc), or PMCCR().OSLO == '0') and OSLockStatus() ERROR RO PMCEID0_EL0 Architectural AArch64 31 0 31 0 31 0 31 0 PMCEID0 Architectural AArch32 31 0 31 0 31 0 31 0 Defines which Common architectural events and Common microarchitectural events are implemented, or counted, using PMU events in the range 0x0000 to 0x001F. For more information about the Common events and the use of the PMCEIDn registers, see 'The PMU event number space and common events'. Use of this register is deprecated. This view of the register was previously called PMCEID0_EL0. PMU PMCEID0 is in the Core power domain. PMCEID0 is a 32-bit register. ID<n> 31 0 31:0 ID[n] corresponds to Common event n. For each bit: When the value of a bit in the field is 1, the corresponding Common event is implemented and counted. Arm recommends that if a Common event is never counted, the value of the corresponding bit is 0.A bit that corresponds to a reserved event number is reserved. The value might be used in a future revision of the architecture to identify an additional Common event. Such an event might be added retrospectively to an earlier version of the PMU architecture, provided the event does not require any additional PMU features and has an event number that can be represented in the PMCEID<n> registers of that earlier version of the PMU architecture. 31 0 0b0 The Common event is not implemented, or not counted. 0b1 The Common event is implemented. AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information. Accessible at offset 0xE20 from PMU 2026-03-26 20:27:25 2026-03_rel