PMCFGR Performance Monitors Configuration Register PMU when FEAT_PMUv3_EXT is implemented and FEAT_PMUv3 is implemented PMU 0xE00 When DoubleLockStatus(), or !IsCorePowered(), or !AllowExternalPMUAccess(addrdesc) ERROR When (FEAT_PMUv3_EXTPMN is not implemented, or !IsMostSecureAccess(addrdesc), or PMCCR().OSLO == '0') and OSLockStatus() ERROR RO PMU 0xE00 When DoubleLockStatus(), or !IsCorePowered(), or !AllowExternalPMUAccess(addrdesc) ERROR When (FEAT_PMUv3_EXTPMN is not implemented, or !IsMostSecureAccess(addrdesc), or PMCCR().OSLO == '0') and OSLockStatus() ERROR RO Contains PMU-specific configuration data. PMU PMCFGR is in the Core power domain. PMCFGR is a: 64-bit register when FEAT_PMUv3_EXT64 is implemented 32-bit register otherwise When FEAT_PMUv3_EXT64 is implemented 63 32 63:32 Reserved, RES0. NCG 31 28 31:28 Defines the number of counter groups implemented, minus one. All other values are reserved. FEAT_PMUv3_ICNTR implements the functionality identified by the value 0b0001. 0b0000 One counter group implemented. 0b0001 Two counter groups implemented. RO 27 23 27:23 Reserved, RES0. SS 22 22 22 Snapshot supported. FEAT_PMUv3_SS implements the functionality identified by the value 1. If FEAT_PMUv3_SS is not implemented, a PMU might include an IMPLEMENTATION DEFINED snapshot mechanism, including one using the IMPLEMENTATION DEFINED registers 0x600-0x7FC and 0xE30-0xE3C. 0b0 Snapshot mechanism not supported. The locations 0x600-0x7FC and 0xE30-0xE3C are IMPLEMENTATION DEFINED. 0b1 Snapshot mechanism supported. If FEAT_PMUv3_SS is implemented, then the following registers are implemented: PMEVCNTSVR<n>_EL1. PMCCNTSVR_EL1. If FEAT_PMUv3_ICNTR is implemented, PMICNTSVR_EL1. PMSSCR_EL1. Otherwise, locations 0x600-0x7FC and 0xE30-0xE3C contain IMPLEMENTATION DEFINED snapshot registers. RO FZO 21 21 21 Freeze-on-overflow supported. FEAT_PMUv3p7 implements the functionality added by the value 1. From Armv8.7, if FEAT_PMUv3 is implemented, the only permitted value is 1. 0b0 Freeze-on-overflow mechanism is not supported. PMCR_EL0.FZO is RES0. 0b1 Freeze-on-overflow mechanism is supported. PMCR_EL0.FZO is RW. RO 20 20 20 Reserved, RES0. UEN 19 19 19 User-mode Enable Register supported. PMUSERENR_EL0 is not visible in the external debug interface, so this bit is RAZ. Reads as 0b0. RO WT 18 18 18 This feature is not supported, so this bit is RAZ. Reads as 0b0. RO NA 17 17 17 This feature is not supported, so this bit is RAZ. Reads as 0b0. RO EX 16 16 16 Export supported. 0b0 PMCR_EL0.X is RES0. 0b1 PMCR_EL0.X is read/write. RO CCD 15 15 15 Cycle counter has prescale. This is RES1 if AArch32 is supported, and RAZ otherwise. 0b0 PMCR_EL0.D is RES0. 0b1 PMCR_EL0.D is read/write. RO CC 14 14 14 Dedicated cycle counter (counter 31) supported. Reads as 0b1. RO SIZE 13 8 13:8 Size of counters, minus one. This field defines the size of the largest counter implemented by the Performance Monitors Unit. From Armv8.0, the largest counter is 64-bits, so the value of this field is 0b111111. This field is used by software to determine the spacing of the counters in the memory-map. From Armv8.0, the counters are a doubleword-aligned addresses. Reads as 0b111111. RO N 7 0 7:0 Number of counters accessible, minus one. All other values are reserved. If FEAT_PMUv3_ICNTR is implemented, then the value 0x00 is not permitted. The count includes: The cycle counter, PMCCNTR_EL0. If FEAT_PMUv3_ICNTR is implemented, the Instruction Counter, PMICNTR_EL0. When FEAT_PMUv3_EXTPMN is implemented and the access to this register is not a Most secure access, the following apply: If FEAT_PMUv3_ICNTR is not implemented, this field reads as the Effective value of PMCCR.EPMN. If FEAT_PMUv3_ICNTR is implemented, this field reads as the Effective value of PMCCR.EPMN plus one. Otherwise, the following apply: If FEAT_PMUv3_ICNTR is not implemented, this field reads as the number of event counters implemented. If FEAT_PMUv3_ICNTR is implemented, this field reads as the number of event counters implemented plus one. For example, if PMCFGR.N == 0x07, then: There are eight counters in total. If FEAT_PMUv3_ICNTR is not implemented, this comprises 7 event counters and the cycle counter. If FEAT_PMUv3_ICNTR is implemented, this comprises 6 event counters, the cycle counter, and the instruction counter. The maximum number of event counters is 31. 0x00 Only PMCCNTR_EL0 accessible. 0x01..0x20 Number of counters accessible, 2 to 33, minus one. RO NCG 31 28 31:28 Defines the number of counter groups implemented, minus one. All other values are reserved. FEAT_PMUv3_ICNTR implements the functionality identified by the value 0b0001. 0b0000 One counter group implemented. 0b0001 Two counter groups implemented. RO 27 23 27:23 Reserved, RES0. SS 22 22 22 Snapshot supported. FEAT_PMUv3_SS implements the functionality identified by the value 1. If FEAT_PMUv3_SS is not implemented, a PMU might include an IMPLEMENTATION DEFINED snapshot mechanism, including one using the IMPLEMENTATION DEFINED registers 0x600-0x7FC and 0xE30-0xE3C. 0b0 Snapshot mechanism not supported. The locations 0x600-0x7FC and 0xE30-0xE3C are IMPLEMENTATION DEFINED. 0b1 Snapshot mechanism supported. If FEAT_PMUv3_SS is implemented, then the following registers are implemented: PMEVCNTSVR<n>_EL1. PMCCNTSVR_EL1. If FEAT_PMUv3_ICNTR is implemented, PMICNTSVR_EL1. PMSSCR_EL1. Otherwise, locations 0x600-0x7FC and 0xE30-0xE3C contain IMPLEMENTATION DEFINED snapshot registers. RO FZO 21 21 21 Freeze-on-overflow supported. FEAT_PMUv3p7 implements the functionality added by the value 1. From Armv8.7, if FEAT_PMUv3 is implemented, the only permitted value is 1. 0b0 Freeze-on-overflow mechanism is not supported. PMCR_EL0.FZO is RES0. 0b1 Freeze-on-overflow mechanism is supported. PMCR_EL0.FZO is RW. RO 20 20 20 Reserved, RES0. UEN 19 19 19 User-mode Enable Register supported. PMUSERENR_EL0 is not visible in the external debug interface, so this bit is RAZ. Reads as 0b0. RO WT 18 18 18 This feature is not supported, so this bit is RAZ. Reads as 0b0. RO NA 17 17 17 This feature is not supported, so this bit is RAZ. Reads as 0b0. RO EX 16 16 16 Export supported. 0b0 PMCR_EL0.X is RES0. 0b1 PMCR_EL0.X is read/write. RO CCD 15 15 15 Cycle counter has prescale. This is RES1 if AArch32 is supported, and RAZ otherwise. 0b0 PMCR_EL0.D is RES0. 0b1 PMCR_EL0.D is read/write. RO CC 14 14 14 Dedicated cycle counter (counter 31) supported. Reads as 0b1. RO SIZE 13 8 13:8 Size of counters, minus one. This field defines the size of the largest counter implemented by the Performance Monitors Unit. From Armv8.0, the largest counter is 64-bits, so the value of this field is 0b111111. This field is used by software to determine the spacing of the counters in the memory-map. From Armv8.0, the counters are a doubleword-aligned addresses. Reads as 0b111111. RO N 7 0 7:0 Number of counters accessible, minus one. All other values are reserved. If FEAT_PMUv3_ICNTR is implemented, then the value 0x00 is not permitted. The count includes: The cycle counter, PMCCNTR_EL0. If FEAT_PMUv3_ICNTR is implemented, the Instruction Counter, PMICNTR_EL0. When FEAT_PMUv3_EXTPMN is implemented and the access to this register is not a Most secure access, the following apply: If FEAT_PMUv3_ICNTR is not implemented, this field reads as the Effective value of PMCCR.EPMN. If FEAT_PMUv3_ICNTR is implemented, this field reads as the Effective value of PMCCR.EPMN plus one. Otherwise, the following apply: If FEAT_PMUv3_ICNTR is not implemented, this field reads as the number of event counters implemented. If FEAT_PMUv3_ICNTR is implemented, this field reads as the number of event counters implemented plus one. For example, if PMCFGR.N == 0x07, then: There are eight counters in total. If FEAT_PMUv3_ICNTR is not implemented, this comprises 7 event counters and the cycle counter. If FEAT_PMUv3_ICNTR is implemented, this comprises 6 event counters, the cycle counter, and the instruction counter. The maximum number of event counters is 31. 0x00 Only PMCCNTR_EL0 accessible. 0x01..0x20 Number of counters accessible, 2 to 33, minus one. RO When FEAT_PMUv3_EXT64 is implemented AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information. [63:0] Accessible at offset 0xE00 from PMU When FEAT_PMUv3_EXT64 is implemented [31:0] Accessible at offset 0xE00 from PMU When FEAT_PMUv3_EXT32 is implemented 2026-03-26 20:27:25 2026-03_rel