PMCGCR0 Counter Group Configuration Register 0 PMU when FEAT_PMUv3_ICNTR is implemented, FEAT_PMUv3_EXT is implemented, and FEAT_PMUv3 is implemented PMU 0xCE0 When DoubleLockStatus(), or !IsCorePowered(), or !AllowExternalPMUAccess(addrdesc) ERROR When (FEAT_PMUv3_EXTPMN is not implemented, or !IsMostSecureAccess(addrdesc), or PMCCR().OSLO == '0') and OSLockStatus() ERROR RO PMU 0xCE0 When DoubleLockStatus(), or !IsCorePowered(), or !AllowExternalPMUAccess(addrdesc) ERROR When (FEAT_PMUv3_EXTPMN is not implemented, or !IsMostSecureAccess(addrdesc), or PMCCR().OSLO == '0') and OSLockStatus() ERROR RO Encodes the number of counters accessible. PMU PMCGCR0 is in the Core power domain. PMCGCR0 is a: 64-bit register when FEAT_PMUv3_EXT64 is implemented 32-bit register otherwise When FEAT_PMUv3_EXT64 is implemented 63 16 63:16 Reserved, RES0. CG1NC 15 8 15:8 Number of counters in group 1, which comprises the instruction counter PMICNTR_EL0. Other values are reserved. 0x01 PMICNTR_EL0 implemented. RO CG0NC 7 0 7:0 Number of counters in group 0, which comprises the event counters PMEVCNTR<n>_EL0 and the cycle counter PMCCNTR_EL0. When FEAT_PMUv3_EXTPMN is implemented and the external access to this register is not a Most secure access, this field reads as the Effective value of PMCCR.EPMN plus one. Otherwise, this field reads as the number of event counters implemented plus one. This field has an IMPLEMENTATION DEFINED value. RO 31 16 31:16 Reserved, RES0. CG1NC 15 8 15:8 Number of counters in group 1, which comprises the instruction counter PMICNTR_EL0. Other values are reserved. 0x01 PMICNTR_EL0 implemented. RO CG0NC 7 0 7:0 Number of counters in group 0, which comprises the event counters PMEVCNTR<n>_EL0 and the cycle counter PMCCNTR_EL0. When FEAT_PMUv3_EXTPMN is implemented and the external access to this register is not a Most secure access, this field reads as the Effective value of PMCCR.EPMN plus one. Otherwise, this field reads as the number of event counters implemented plus one. This field has an IMPLEMENTATION DEFINED value. RO When FEAT_PMUv3_EXT64 is implemented [31:0] Accessible at offset 0xCE0 from PMU When FEAT_PMUv3_EXT32 is implemented [63:0] Accessible at offset 0xCE0 from PMU When FEAT_PMUv3_EXT64 is implemented 2026-03-26 20:27:25 2026-03_rel