PMCID1SR CONTEXTIDR_EL1 Sample Register PMU when FEAT_PMUv3_EXT32 is implemented and FEAT_PCSRv8p2 is implemented PMU 0x208 When DoubleLockStatus() or !IsCorePowered() ERROR When (FEAT_PMUv3_EXTPMN is not implemented, or !IsMostSecureAccess(addrdesc), or PMCCR().OSLO == '0') and OSLockStatus() ERROR RO PMU 0x228 When DoubleLockStatus() or !IsCorePowered() ERROR When (FEAT_PMUv3_EXTPMN is not implemented, or !IsMostSecureAccess(addrdesc), or PMCCR().OSLO == '0') and OSLockStatus() ERROR RO PC Sample-based Profiling Extension register that contains the sampled value of CONTEXTIDR_EL1, captured on reading PMPCSR[31:0]. PMU PMCID1SR is in the Core power domain. PMCID1SR is a 32-bit register. CONTEXTIDR_EL1 31 0 31:0 Context ID. The value of CONTEXTIDR that is associated with the most recent PMPCSR sample. When the most recent PMPCSR sample is generated: If EL1 is using AArch64, then the Context ID is sampled from CONTEXTIDR_EL1. If EL1 is using AArch32, then the Context ID is sampled from CONTEXTIDR. If EL3 is implemented and is using AArch32, then CONTEXTIDR is a banked register and this register samples the current banked copy of CONTEXTIDR for the Security state that is associated with the most recent PMPCSR sample. Because the value written to this register is an indirect read of CONTEXTIDR, it is CONSTRAINED UNPREDICTABLE whether this register is set to the original or new value if PMPCSR samples: An instruction that writes to CONTEXTIDR. The next Context synchronization event. Any instruction executed between these two instructions. AU If FEAT_PCSRv8p2 and FEAT_PMUv3_EXT64 are implemented, then the same content is present in the same locations, and can be accessed using PMCCIDSR[31:0] or PMCVIDSR[31:0]. IMPLEMENTATION DEFINED extensions to external debug might make the value of this register UNKNOWN, see 'Permitted behavior that might make the PC Sample-based profiling registers UNKNOWN'. Accessible at offset 0x208 from PMU Accessible at offset 0x228 from PMU 2026-03-26 20:27:25 2026-03_rel