PMCIDR1 Performance Monitors Component Identification Register 1 PMU when FEAT_PMUv3_EXT is implemented and an implementation implements PMCIDR1 PMU 0xFF4 When FEAT_DoPD is implemented and !IsCorePowered() ERROR RO Provides information to identify a Performance Monitor component. For more information, see 'About the Component Identification scheme'. PMU If FEAT_DoPD is implemented, this register is in the Core power domain. If FEAT_DoPD is not implemented, this register is in the Debug power domain. This register is required for CoreSight compliance. PMCIDR1 is a 32-bit register. 31 8 31:8 Reserved, RES0. CLASS 7 4 7:4 Component class. Other values are defined by the CoreSight Architecture. This field reads as 0x9. 0b1001 CoreSight component. RO PRMBL_1 3 0 3:0 Preamble. Reads as 0b0000. RO Accessible at offset 0xFF4 from PMU 2026-03-26 20:27:25 2026-03_rel