PMCR_EL0 Performance Monitors Control Register PMU when FEAT_PMUv3_EXT is implemented and FEAT_PMUv3 is implemented PMU 0xE04 When DoubleLockStatus(), or !IsCorePowered(), or !AllowExternalPMUAccess(addrdesc) ERROR When (FEAT_PMUv3_EXTPMN is not implemented, or !IsMostSecureAccess(addrdesc), or PMCCR().OSLO == '0') and OSLockStatus() ERROR When SoftwareLockStatus(addrdesc) RO RW PMU 0xE10 When DoubleLockStatus(), or !IsCorePowered(), or !AllowExternalPMUAccess(addrdesc) ERROR When (FEAT_PMUv3_EXTPMN is not implemented, or !IsMostSecureAccess(addrdesc), or PMCCR().OSLO == '0') and OSLockStatus() ERROR RW PMCR_EL0 Architectural AArch64 63 32 63 32 63 32 63 32 when FEAT_PMUv3_EXT64 is implemented PMCR_EL0 Architectural AArch64 31 0 31 0 31 0 31 0 PMCR Architectural AArch32 10 0 10 0 10 0 10 0 Configures and controls the Performance Monitors counters. PMU PMCR_EL0 is in the Core power domain. This register is only partially mapped to the internal PMCR System register. An external agent must use other means to discover the information held in PMCR[31:11], such as accessing PMCFGR and the ID registers. PMCR_EL0 is a: 64-bit register when FEAT_PMUv3_EXT64 is implemented 32-bit register otherwise When FEAT_PMUv3_EXT64 is implemented 63 33 63:33 Reserved, RES0. FZS 32 32 0 Freeze-on-SPE event. Stop counters when PMBLIMITR_EL1.{PMFZ,E} is {1,1} and profiling is stopped. The pseudocode function SPEProfilingStopped() describes when profiling is stopped. The counters affected by this field are: The event counters in the first range. If FEAT_PMUv3_ICNTR is implemented, the instruction counter PMICNTR_EL0. If FEAT_SPE_DPFZS is implemented and PMCR_EL0.DP is 1, the cycle counter PMCCNTR_EL0. Other event counters are not affected by this field. When FEAT_SPE_DPFZS is not implemented or PMCR_EL0.DP is 0, PMCCNTR_EL0 is not affected by this field. For more information about event counter ranges, see MDCR_EL2.HPMN. 0b0 Do not freeze on a Statistical Profiling Buffer Management event. 0b1 Affected counters do not count following a Statistical Profiling Buffer Management event. '0' AU When FEAT_SPEv1p2 is implemented 32 32 32 Reserved, RES0. Otherwise 31 11 31:11 Reserved, RAZ/WI. Hardware must implement this field as RAZ/WI. Software must not rely on the register reading as zero, and must use a read-modify-write sequence to write to the register. 10 10 10 Reserved, RES0. FZO 9 9 0 Freeze-on-overflow. Stop event counters on overflow. The counters affected by this field are: The event counters in the first range. If FEAT_PMUv3_ICNTR is implemented, the instruction counter PMICNTR_EL0. If PMCR_EL0.DP is 1, the cycle counter PMCCNTR_EL0. Other event counters are not affected by this field. When PMCR_EL0.DP is 0, PMCCNTR_EL0 is not affected by this field. For more information about event counter ranges, see MDCR_EL2.HPMN. 0b0 Do not freeze on overflow. 0b1 Affected counters do not count when any of the following applies: For any event counter PMEVCNTR<m>_EL0 in the first range, PMOVSCLR_EL0[m] is 1. FEAT_PMUv3_ICNTR is implemented and PMOVSCLR_EL0.F0 is 1. AU When FEAT_PMUv3p7 is implemented 9 9 9 Reserved, RES0. Otherwise 8 8 8 Reserved, RES0. LP 7 7 0 Long event counter enable. Determines when unsigned overflow is recorded by PMOVSCLR_EL0.P[n]. When FEAT_EBEP is implemented and the PMU Profiling exception is enabled, the Effective value of this field is 1. The counters affected by this field are the event counters in the first range. For more information about event counter ranges, see MDCR_EL2.HPMN. Other event counters and PMCCNTR_EL0 are not affected by this field. When FEAT_PMUv3_ICNTR is implemented, PMICNTR_EL0 is not affected by this field. 0b0 Event counter overflow on increment that causes unsigned overflow of PMEVCNTR<n>_EL0[31:0]. 0b1 Event counter overflow on increment that causes unsigned overflow of PMEVCNTR<n>_EL0[63:0]. '0' AU When FEAT_PMUv3p5 is implemented 7 7 7 Reserved, RES0. Otherwise LC 6 6 0 Long cycle counter enable. Determines when unsigned overflow is recorded by PMOVSCLR_EL0.C. When FEAT_EBEP is implemented and the PMU Profiling exception is enabled, the Effective value of this field is 1. Arm deprecates use of PMCR_EL0.LC = 0. 0b0 Cycle counter overflow on increment that causes unsigned overflow of PMCCNTR_EL0[31:0]. 0b1 Cycle counter overflow on increment that causes unsigned overflow of PMCCNTR_EL0[63:0]. AU When FEAT_AA32 is implemented 6 6 6 Reserved, RES1. Otherwise DP 5 5 0 Disable cycle counter when event counting is prohibited. The conditions when this field disables the cycle counter are the same as when event counting by an event counter in the first range is prohibited or frozen. For more information about event counter ranges, see MDCR_EL2.HPMN. If FEAT_PMUv3p7 and FEAT_SPEv1p2 are implemented, meaning PMCR_EL0.FZS is implemented, and FEAT_SPE_DPFZS is not implemented, then cycle counting by PMCCNTR_EL0 is not affected by PMCR_EL0.FZS. For more information, see 'Prohibiting event and cycle counting'. 0b0 Cycle counting by PMCCNTR_EL0 is not affected by this mechanism. 0b1 Cycle counting by PMCCNTR_EL0 is disabled in prohibited regions and when event counting is frozen: If FEAT_PMUv3p1 is implemented, EL2 is implemented, and MDCR_EL2.HPMD or HDCR.HPMD is 1, then cycle counting by PMCCNTR_EL0 is disabled at EL2. If FEAT_SPE_DPFZS is implemented and event counting is frozen by PMCR_EL0.FZS, then cycle counting by PMCCNTR_EL0 is disabled. If FEAT_PMUv3p7 is implemented and event counting is frozen by PMCR_EL0.FZO, then cycle counting by PMCCNTR_EL0 is disabled. If FEAT_PMUv3p7 is implemented, EL3 is implemented and using AArch64, and MDCR_EL3.MPMX is 1, then cycle counting by PMCCNTR_EL0 is disabled at EL3. If EL3 is implemented, MDCR_EL3.SPME or SDCR.SPME is 0, and one of FEAT_PMUv3p7 is not implemented, EL3 is using AArch32, or MDCR_EL3.MPMX is 0, then cycle counting by PMCCNTR_EL0 is disabled at EL3 and in Secure state. '0' AU When EL3 is implemented, or (FEAT_PMUv3p1 is implemented and EL2 is implemented), or FEAT_PMUv3p7 is implemented, or FEAT_SPE_DPFZS is implemented 5 5 5 Reserved, RES0. Otherwise X 4 4 0 Enable export of events in an IMPLEMENTATION DEFINED PMU event export bus. This field enables the exporting of events over an IMPLEMENTATION DEFINED PMU event export bus to another device. No events are exported when counting is prohibited. This field does not affect the generation of Performance Monitors overflow interrupt requests or signaling to a cross-trigger interface (CTI) that can be implemented as signals exported from the PE. If FEAT_ETE is implemented, this field does not affect the use of PMU events as an External Input by the trace unit. If FEAT_ETMv4 is implemented, this field does affect the use of PMU events as an External Input by the trace unit. 0b0 Do not export events. 0b1 Export events where not prohibited. '0' AU When the implementation includes a PMU event export bus 4 4 4 Reserved, RAZ/WI. Otherwise D 3 3 0 Clock divider. If the Effective value of PMCR_EL0.LC is 1, then this field is ignored and the cycle counter counts every clock cycle. Arm deprecates use of PMCR_EL0.D = 1. 0b0 When enabled, PMCCNTR_EL0 counts every clock cycle. 0b1 When enabled, PMCCNTR_EL0 counts once every 64 clock cycles. '0' AU When FEAT_AA32 is implemented 3 3 3 Reserved, RES0. Otherwise C 2 2 2 Cycle counter reset. The effects of writing to this field are: Resetting PMCCNTR_EL0 does not change the cycle counter overflow field. The value of PMCR_EL0.LC is ignored, and bits [63:0] of the cycle counter are reset. 0b0 No action. 0b1 Reset PMCCNTR_EL0 to zero. WO/RAZ P 1 1 1 Event counter reset. The event counters affected by this field are: If FEAT_PMUv3_EXTPMN is implemented and the access to this register is a Most secure access, all event counters. Otherwise, only event counters in the first and second ranges. Writes to this field do not affect other event counters, the cycle counter PMCCNTR_EL0, or the instruction counter PMICNTR_EL0. For more information about event counter ranges, see MDCR_EL2.HPMN. Resetting the event counters does not change the event counter overflow fields. If FEAT_PMUv3p5 is implemented, the values of MDCR_EL2.HLP or HDCR.HLP and PMCR_EL0.LP are ignored, and bits [63:0] of all affected event counters are reset. 0b0 No action. 0b1 Reset all affected event counters PMEVCNTR<n>_EL0 to zero. WO/RAZ E 0 0 0 Enable. The counters affected by this field are: The event counters in the first range. For more information about event counter ranges, see MDCR_EL2.HPMN. If FEAT_PMUv3_ICNTR is implemented, the instruction counter PMICNTR_EL0. The cycle counter PMCCNTR_EL0. Other event counters are not affected by this field. 0b0 Affected counters are disabled and do not count. 0b1 Affected counters are enabled by PMCNTENSET_EL0. '0' 31 11 31:11 Reserved, RAZ/WI. Hardware must implement this field as RAZ/WI. Software must not rely on the register reading as zero, and must use a read-modify-write sequence to write to the register. 10 10 10 Reserved, RES0. FZO 9 9 0 Freeze-on-overflow. Stop event counters on overflow. The counters affected by this field are: The event counters in the first range. If FEAT_PMUv3_ICNTR is implemented, the instruction counter PMICNTR_EL0. If PMCR_EL0.DP is 1, the cycle counter PMCCNTR_EL0. Other event counters are not affected by this field. When PMCR_EL0.DP is 0, PMCCNTR_EL0 is not affected by this field. For more information about event counter ranges, see MDCR_EL2.HPMN. 0b0 Do not freeze on overflow. 0b1 Affected counters do not count when any of the following applies: For any event counter PMEVCNTR<m>_EL0 in the first range, PMOVSCLR_EL0[m] is 1. FEAT_PMUv3_ICNTR is implemented and PMOVSCLR_EL0.F0 is 1. AU When FEAT_PMUv3p7 is implemented 9 9 9 Reserved, RES0. Otherwise 8 8 8 Reserved, RES0. LP 7 7 0 Long event counter enable. Determines when unsigned overflow is recorded by PMOVSCLR_EL0.P[n]. When FEAT_EBEP is implemented and the PMU Profiling exception is enabled, the Effective value of this field is 1. The counters affected by this field are the event counters in the first range. For more information about event counter ranges, see MDCR_EL2.HPMN. Other event counters and PMCCNTR_EL0 are not affected by this field. When FEAT_PMUv3_ICNTR is implemented, PMICNTR_EL0 is not affected by this field. 0b0 Event counter overflow on increment that causes unsigned overflow of PMEVCNTR<n>_EL0[31:0]. 0b1 Event counter overflow on increment that causes unsigned overflow of PMEVCNTR<n>_EL0[63:0]. '0' AU When FEAT_PMUv3p5 is implemented 7 7 7 Reserved, RES0. Otherwise LC 6 6 0 Long cycle counter enable. Determines when unsigned overflow is recorded by PMOVSCLR_EL0.C. When FEAT_EBEP is implemented and the PMU Profiling exception is enabled, the Effective value of this field is 1. Arm deprecates use of PMCR_EL0.LC = 0. 0b0 Cycle counter overflow on increment that causes unsigned overflow of PMCCNTR_EL0[31:0]. 0b1 Cycle counter overflow on increment that causes unsigned overflow of PMCCNTR_EL0[63:0]. AU When FEAT_AA32 is implemented 6 6 6 Reserved, RES1. Otherwise DP 5 5 0 Disable cycle counter when event counting is prohibited. The conditions when this field disables the cycle counter are the same as when event counting by an event counter in the first range is prohibited or frozen. For more information about event counter ranges, see MDCR_EL2.HPMN. If FEAT_PMUv3p7 and FEAT_SPEv1p2 are implemented, meaning PMCR_EL0.FZS is implemented, and FEAT_SPE_DPFZS is not implemented, then cycle counting by PMCCNTR_EL0 is not affected by PMCR_EL0.FZS. For more information, see 'Prohibiting event and cycle counting'. 0b0 Cycle counting by PMCCNTR_EL0 is not affected by this mechanism. 0b1 Cycle counting by PMCCNTR_EL0 is disabled in prohibited regions and when event counting is frozen: If FEAT_PMUv3p1 is implemented, EL2 is implemented, and MDCR_EL2.HPMD or HDCR.HPMD is 1, then cycle counting by PMCCNTR_EL0 is disabled at EL2. If FEAT_SPE_DPFZS is implemented and event counting is frozen by PMCR_EL0.FZS, then cycle counting by PMCCNTR_EL0 is disabled. If FEAT_PMUv3p7 is implemented and event counting is frozen by PMCR_EL0.FZO, then cycle counting by PMCCNTR_EL0 is disabled. If FEAT_PMUv3p7 is implemented, EL3 is implemented and using AArch64, and MDCR_EL3.MPMX is 1, then cycle counting by PMCCNTR_EL0 is disabled at EL3. If EL3 is implemented, MDCR_EL3.SPME or SDCR.SPME is 0, and one of FEAT_PMUv3p7 is not implemented, EL3 is using AArch32, or MDCR_EL3.MPMX is 0, then cycle counting by PMCCNTR_EL0 is disabled at EL3 and in Secure state. '0' AU When EL3 is implemented, or (FEAT_PMUv3p1 is implemented and EL2 is implemented), or FEAT_PMUv3p7 is implemented, or FEAT_SPE_DPFZS is implemented 5 5 5 Reserved, RES0. Otherwise X 4 4 0 Enable export of events in an IMPLEMENTATION DEFINED PMU event export bus. This field enables the exporting of events over an IMPLEMENTATION DEFINED PMU event export bus to another device. No events are exported when counting is prohibited. This field does not affect the generation of Performance Monitors overflow interrupt requests or signaling to a cross-trigger interface (CTI) that can be implemented as signals exported from the PE. If FEAT_ETE is implemented, this field does not affect the use of PMU events as an External Input by the trace unit. If FEAT_ETMv4 is implemented, this field does affect the use of PMU events as an External Input by the trace unit. 0b0 Do not export events. 0b1 Export events where not prohibited. '0' AU When the implementation includes a PMU event export bus 4 4 4 Reserved, RAZ/WI. Otherwise D 3 3 0 Clock divider. If the Effective value of PMCR_EL0.LC is 1, then this field is ignored and the cycle counter counts every clock cycle. Arm deprecates use of PMCR_EL0.D = 1. 0b0 When enabled, PMCCNTR_EL0 counts every clock cycle. 0b1 When enabled, PMCCNTR_EL0 counts once every 64 clock cycles. '0' AU When FEAT_AA32 is implemented 3 3 3 Reserved, RES0. Otherwise C 2 2 2 Cycle counter reset. The effects of writing to this field are: Resetting PMCCNTR_EL0 does not change the cycle counter overflow field. The value of PMCR_EL0.LC is ignored, and bits [63:0] of the cycle counter are reset. 0b0 No action. 0b1 Reset PMCCNTR_EL0 to zero. WO/RAZ P 1 1 1 Event counter reset. The event counters affected by this field are: If FEAT_PMUv3_EXTPMN is implemented and the access to this register is a Most secure access, all event counters. Otherwise, only event counters in the first and second ranges. Writes to this field do not affect other event counters, the cycle counter PMCCNTR_EL0, or the instruction counter PMICNTR_EL0. For more information about event counter ranges, see MDCR_EL2.HPMN. Resetting the event counters does not change the event counter overflow fields. If FEAT_PMUv3p5 is implemented, the values of MDCR_EL2.HLP or HDCR.HLP and PMCR_EL0.LP are ignored, and bits [63:0] of all affected event counters are reset. 0b0 No action. 0b1 Reset all affected event counters PMEVCNTR<n>_EL0 to zero. WO/RAZ E 0 0 0 Enable. The counters affected by this field are: The event counters in the first range. For more information about event counter ranges, see MDCR_EL2.HPMN. If FEAT_PMUv3_ICNTR is implemented, the instruction counter PMICNTR_EL0. The cycle counter PMCCNTR_EL0. Other event counters are not affected by this field. 0b0 Affected counters are disabled and do not count. 0b1 Affected counters are enabled by PMCNTENSET_EL0. '0' When FEAT_PMUv3_EXT64 is implemented Accessible at offset 0xE04 from PMU When FEAT_PMUv3_EXT32 is implemented Accessible at offset 0xE10 from PMU When FEAT_PMUv3_EXT64 is implemented 2026-03-26 20:27:25 2026-03_rel